GS815018AB GSI [GSI Technology], GS815018AB Datasheet - Page 6

• Manufacturer Part Number: GS815018AB
• Description: 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
• Manufacturer: GSI [GSI Technology]

Register-Register Late Write, Pipelined Read Truth Table
Rev: 1.05 10/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
3.
4.
5.
6.
CK
X
↑
↑
↑
↑
↑
↑
If one or more Bx = 0, then B = “T” else B = “F”.
“1” = input “high”; “0” = input “low”; “X” = input “don’t care”.
“***” indicates that the DQ input requirement/output state and CQ output state are determined by the previous operation.
DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces
of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
ZZ
1
0
0
0
0
0
0
SS
X
1
0
0
0
0
0
SW
X
X
1
1
0
0
0
Bx
X
X
X
X
X
0
1
G
X
X
X
X
X
1
0
Sleep (Power Down) mode
Current Operation
Write Bytes with Bx = 0
6/25
Write All Bytes
Write (Abort)
Deselect
Read
Read
GS815018/36AB-357/333/300/250
Hi-Z/
Hi-Z
DQ
(t
***
***
***
***
***
n
)
© 2003, GSI Technology
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(t
Q(t
D(t
D(t
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
n+1
n
n
n
)
)
)
)