GS815018AB GSI [GSI Technology], GS815018AB Datasheet - Page 5

• Manufacturer Part Number: GS815018AB
• Description: 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
• Manufacturer: GSI [GSI Technology]

Write Operations
Write operations are initiated when the write enable input signal (SW) and chip select (SS) are captured at logic 0 on a rising edge
of the K clock (and falling edge of the K clock).
Late Write
In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late
Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT
SRAMs.
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Byte write control
inputs are captured by the same clock edge used to capture SW.
Example of x36 Byte Write Truth Table
Rev: 1.05 10/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Write all Bytes
Write Byte A
Write Byte B
Write Byte C
Write Byte D
Write Abort
Function
Read
5/25
SW
H
L
L
L
L
L
L
Ba
X
H
H
H
H
L
L
GS815018/36AB-357/333/300/250
Bb
H
H
H
H
X
L
L
Bc
H
H
H
H
X
L
L
© 2003, GSI Technology
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Bd
X
H
H
H
H
L
L