AM29BDS128HD8VFI AMD [Advanced Micro Devices], AM29BDS128HD8VFI Datasheet - Page 65
AM29BDS128HD8VFI
Manufacturer Part Number
AM29BDS128HD8VFI
Description
128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM29BDS128HD8VFI.pdf
(89 pages)
- Current page: 65 of 89
- Download datasheet (2Mb)
AC CHARACTERISTICS
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence
has been written with A18=0; device will output RDY with valid data.
1) RDY goes low during the two-cycle latency during a boundary crossing.
2) RDY stays high when a burst sequence crosses no boundaries.
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence
has been written with A18=0; device will output RDY with valid data.
1) Burst suspend during the initial synchronous access
2) Burst suspend after one clock cycle following the initial synchronous access
May 10, 2006 27024B3
Addresses
Addresses
Data(2)
Data(1)
RDY(2)
RDY(1)
OE#(1)
Data(1)
RDY(1)
OE#(2)
RDY(2)
Data(2)
AVD#
OE#
CLK
AVD#
CLK
A(n)
Figure 26. Standard Handshake Burst Suspend at or after Initial Access
Figure 25. Standard Handshake Burst Suspend Prior to Initial Access
A(n)
1
1
2
2
t
ACC
t
3
ACC
3
4
4
Am29BDS128H/Am29BDS640H
t
OES
5
D A T A
t
5
OES
Suspend
t
t
6
RACC
RACC
6
t
CKA
7
t
S H E E T
RACC
D(n)
D(n)
Suspend
7
t
OES
x
t
RACC
t
CKZ
D(n+1)
8
Resume
t
x+1
OES
t
CKA
D(n)
D(n)
t
RACC
9
t
RACC
x+2
D(n+1)
D(n+1)
x+3
D(n+2)
D(n+2)
x+4
x
D(n+3)
t
RACC
t
RACC
3F
x+5
Resume
x+1
t
OES
D(n+4)
t
CKA
3F
D(n+1)
D(n)
x+6
x+2
D(n+5)
D(3F)
D(n+1)
D(n+2)
x+7
x+3
D(n+6)
D(40)
x+8
63
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