EVAL-ADV7320EB AD [Analog Devices], EVAL-ADV7320EB Datasheet - Page 38

• Manufacturer Part Number: EVAL-ADV7320EB
• Description: Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
• Manufacturer: AD [Analog Devices]

ADV7320/ADV7321
INPUT CONFIGURATION
When 10-bit input data is applied, the following bits must be set
to 1:
Address 0x13, Bit 2 (HD 10-bit enable)
Address 0x48, Bit 4 (SD 10-bit enable)
Note that the ADV7320 defaults to simultaneous standard
definition and progressive scan upon power-up (Address[0x01]:
Input Mode = 011).
STANDARD DEFINITION ONLY
Address[0x01]: Input Mode = 000
The 8-/10-bit, multiplexed input data is input on Pins S9 to S0
(or Pins Y9 to Y0, depending on Register Address 0x01, Bit 7),
with S0 being the LSB in 10-bit input mode (see Table 21). Input
standards supported are ITU-R BT.601/656. In 16-/20-bit input
mode, the Y pixel data is input on Pins S9 to S2 and CrCb data
is input on Pins Y9 to Y2 (see Table 21).
16-/20-Bit Mode Operation
When Register 0x01 Bit 7 = 0, CrCb data is input on the Y bus
and Y data is input on the S bus. When Register 0x01 Bit 7 = 1,
CrCb data is input on the C bus and Y data is input on Y bus.
The 27 MHz clock input must be input on Pin CLKIN_A. Input
sync signals are input on the S_VSYNC , S_HSYNC , and
S_BLANK pins.
Table 21. SD 8-/10-Bit and 16-/20-Bit Configuration
Parameter
Register 0x01, Bit 7 = 0
Register 0x01, Bit 7 = 1
Y Bus
S Bus
C Bus
Y Bus
S Bus
C Bus
*SELECTED BY ADDRESS 0x01 BIT 7
DECODER
MPEG2
YCrCb
Figure 49. SD Only Input Mode
27MHz
10
8-/10-Bit Mode
656/601, YCrCb
656/601, YCrCb
3
S_VSYNC,
S_HSYNC,
S_BLANK
CLKIN_A
S[9:0] OR Y[9:0]*
ADV7320/
ADV7321
Configuration
16-/20-Bit Mode
CrCb
Y
Y
CrCb
Rev. 0 | Page 38 of 88
PROGRESSIVE SCAN ONLY OR HDTV ONLY
Address[0x01]: Input Mode = 001 or 010, Respectively
YCrCb progressive scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data is
input on Pins Y9 to Y0 and the CrCb data is input on Pins C9 to
C0. In 4:4:4 input mode, Y data is input on Pins Y9 to Y0, Cb data
is input on Pins C9 to C0, and Cr data is input on Pins S9 to S0.
If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M
(720p), SMPTE 240M (1035i), or BTA-T1004/1362, the async
timing mode must be used. RGB data can only be input in
4:4:4 format in PS or HDTV input modes when HD RGB input
is enabled. G data is input on Pins Y9 to Y0, R data is input on
Pins S9 to S0, and B data is input on Pins C9 to C0. The clock
signal must be input on Pin CLKIN_A.
SIMULTANEOUS STANDARD DEFINITION AND
PROGRESSIVE SCAN OR HDTV
Address[0x01]: Input Mode 011 (SD 10-Bit, PS 20-Bit) or 101
(SD and HD, SD Oversampled), 110 (SD and HD, HD
Oversampled), Respectively
YCrCb PS and HD data must be input in 4:2:2 format. In 4:2:2
input mode, the HD Y data is input on Pins Y9 to Y0 and the
HD CrCb data is input on Pins C9 to C0. If PS 4:2:2 data is
interleaved onto a single 10-bit bus, Pins Y9 to Y0 are used for
the input port. The input data is to be input at 27 MHz, with the
data being clocked upon the rising and falling edges of the input
clock. The input mode register at Address 0x01 is set
accordingly. If the YCrCb data does not conform to SMPTE
293M (525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i),
SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004,
the async timing mode must be used.
The 8- or 10-bit standard definition data must be compliant
with ITU-R BT.601/656 in 4:2:2 format. Standard definition
data is input on Pins S9 to S0, with S0 being the LSB. Using
8-bit input format, the data is input on Pins S9 to S2. The clock
input for SD must be input on CLKIN_A, and the clock input
for HD must be input on CLKIN_B. Synchronization signals are
INTERLACED TO
PROGRESSIVE
DECODER
MPEG2
YCrCb
Figure 50. Progressive Scan Input Mode
Cb
Cr
Y
27MHz
10
10
10
3
P_HSYNC,
P_BLANK
CLKIN_A
C[9:0]
S[9:0]
Y[9:0]
P_VSYNC,
ADV7320/
ADV7321