EVAL-ADV7320EB AD [Analog Devices], EVAL-ADV7320EB Datasheet - Page 80
EVAL-ADV7320EB
Manufacturer Part Number
EVAL-ADV7320EB
Description
Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
Manufacturer
AD [Analog Devices]
Datasheet
1.EVAL-ADV7320EB.pdf
(88 pages)
- Current page: 80 of 88
- Download datasheet (2Mb)
ADV7320/ADV7321
MODE 3—MASTER/SLAVE OPTION
(TIMING REGISTER 0 TR0 =
X X X X X 1 1 0 OR X X X X X 1 1 1)
In this mode, the ADV7320/ADV7321 accept or generate hori-
zontal sync and odd/even field signals. When HSYNC is high, a
transition of the field input indicates a new frame, i.e., vertical
retrace. The BLANK signal is optional. When the BLANK input
is disabled, ADV7320/ADV7321 automatically blank all
normally blank lines as per CCIR-624. HSYNC , BLANK , and
VSYNC are output in master mode and input in slave mode on
S_VSYNC , S_BLANK , and S_VSYNC , respectively.
HSYNC
BLANK
HSYNC
BLANK
FIELD
FIELD
HSYNC
BLANK
HSYNC
BLANK
FIELD
FIELD
522
260
DISPLAY
622
309
DISPLAY
DISPLAY
DISPLAY
523
261
623
310
524
262
624
311
EVEN FIELD
EVEN FIELD
263
525
625
312
264
ODD FIELD
1
ODD FIELD
ODD FIELD
265
EVEN FIELD
313
2
1
EVEN FIELD
266
3
314
2
Figure 120. SD Timing Mode 3 (NTSC)
Figure 121. SD Timing Mode 3 (PAL)
ODD FIELD
267
4
315
3
Rev. 0 | Page 80 of 88
268
5
VERTICAL BLANK
VERTICAL BLANK
316
4
VERTICAL BLANK
VERTICAL BLANK
269
6
317
5
270
7
318
271
6
8
272
319
7
9
273
10
320
274
11
21
334
22
283
20
DISPLAY
335
23
284
21
DISPLAY
DISPLAY
336
285
DISPLAY
22
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