AM28F010-120EC AMD [Advanced Micro Devices], AM28F010-120EC Datasheet - Page 10

• Manufacturer Part Number: AM28F010-120EC
• Description: 1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

ERASE, PROGRAM, AND READ MODE
When V
ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.
Write Operations
High voltage must be applied to the V
activate the command register. Data written to the reg-
ister serves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.
The command register does not occupy an addressable
memory location. The register is a latch that stores the
command, along with the address and data information
needed to execute the command. The register is written
by bringing WE# and CE# to V
Addresses are latched on the falling edge of WE#, while
data is latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.
The device requires the OE# pin to be V
erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be V
must be V
command will not be executed.
Notes:
1. Bus operations are defined in Table 1.
2. RA = Address of the memory location to be read.
3. RD = Data read from location RA during read operation.
4. Refer to the appropriate section for algorithms and timing diagrams.
10
Command (Note 4)
Read Memory
Read Auto select
Erase Setup/Erase Write
Erase-Verify
Program Setup/Program
Program-Verify
Reset
EA = Address of the memory location to be read during erase-verify.
PA = Address of the memory location to be programmed.
X = Don’t care.
Addresses are latched on the falling edge of the WE
EVD = Data Read from location EA during erase-verify.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE
PVD = Data read from location PA during program-verify. PA is latched on the Program command.
PP
IL
is equal to 12.0 V ± 5%, the command reg-
. If any pin is not in the correct state a write
IL
IH
, while OE# is at V
, and CE# and WE#
Operation
Table 3. Am28F010 Command Definitions
(Note 1)
Write
Write
Write
Write
Write
Write
Write
PP
IH
pin in order to
for write op-
First Bus Cycle
Address
(Note 2)
#
EA
Am28F010
IH
X
X
X
X
X
X
pulse.
.
Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.
Command Definitions
The contents of the command register default to 00h
(Read Mode) in the absence of high voltage applied to
the V
ory. High voltage on the V
register. Device operations are selected by writing spe-
cific data codes into the command register. Table 3 de-
fines these register commands.
Read Command
Memory contents can be accessed via the read com-
mand when V
00h into the command register. Standard microproces-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.
The command register defaults to 00h (read mode)
upon V
fault helps ensure that inadvertent alteration of the
memory contents does not occur during the V
transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters.
80h or 90h
(Note 3)
00h/FFh
Data
A0h
C0h
FFh
20h
40h
PP
PP
pin. The device operates as a read only mem-
power-up. The 00h (Read Mode) register de-
PP
Operation
(Note 1)
is high. To read from the device, write
Read
Read
Read
Read
Write
Write
Write
#
.
Second Bus Cycle
PP
pin enables the command
Address
(Note 2)
00h/01h
RA
PA
X
X
X
X
(Note 3)
01h/A7h
PP
Data
PVD
EVD
20h
FFh
RD
PD
power