AM28F010-120EC AMD [Advanced Micro Devices], AM28F010-120EC Datasheet - Page 2

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AM28F010-120EC

Manufacturer Part Number
AM28F010-120EC
Description
1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
Manufacturer
AMD [Advanced Micro Devices]
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AM28F010-120EC
Manufacturer:
AMD
Quantity:
20 000
minutes required for EPROM erasure using ultra-violet
light are eliminated.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine
which controls the erase and programming circuitry.
During write cycles, the command register internally
latches address and data needed for the programming
and erase operations. For system design simplifica-
tion, the Am28F010 is designed to support either WE#
or CE# controlled writes. During a system write cycle,
addresses are latched on the falling edge of WE# or
CE# whichever occurs last. Data is latched on the ris-
BLOCK DIAGRAM
PRODUCT SELECTOR GUIDE
2
Family Part Number
Speed Options (V
Max Access Time (ns)
CE
OE
#
#
(E
(G
#
#
A0–A16
) Access (ns)
) Access (ns)
WE
OE
CE
Low V
Detector
V
V
V
PP
CC
SS
#
#
#
CC
CC
= 5.0 V
Command
Register
Control
State
10%)
Program/Erase
Pulse Timer
Voltage Switch
Program
Am28F010
Erase Voltage
Switch
-70
70
70
35
ing edge of WE# or CE# whichever occurs first. To
simplify the following discussion, the WE# pin is used
as the write cycle control pin throughout the rest of
this text. All setup and hold times are with respect to
the WE# signal.
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F010 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are pro-
grammed one byte at a time using the EPROM pro-
gramming mechanism of hot electron injection.
To Array
Output Enable
Chip Enable
Y-Decoder
X-Decoder
Logic
-90
90
90
35
Am28F010
-120
120
120
50
Input/Output
DQ0–DQ7
1,048,576 Bit
Buffers
Cell Matrix
Y-Gating
Latch
Data
-150
150
150
55
11559H-1
-200
200
200
55

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