74VHC573MX Fairchild Semiconductor, 74VHC573MX Datasheet - Page 2

• Manufacturer Part Number: 74VHC573MX
• Description: IC LATCH OCTAL D 3STATE 20SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74VHCr

Specifications of 74VHC573MX

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 4.5ns
• Current - Output High, Low: 8mA, 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Number Of Circuits: 8
• Logic Family: 74VHC
• Polarity: Non-Inverting
• Input Bias Current (max): 4 uA
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Propagation Delay Time: 14.5 ns at 3.3 V, 8.8 ns at 5 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©1993 Fairchild Semiconductor Corporation
74VHC573 Rev. 1.3
Logic Symbol
Truth Table
H
L
X
Z
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
LOW Voltage Level
High Impedance
OE
Immaterial
HIGH Voltage Level
H
L
L
L
Inputs
LE
H
H
X
L
IEEE/IEC
D
H
X
X
L
Outputs
O
O
H
L
Z
n
0
2
Functional Description
The VHC573 contains eight D-type latches with
3-STATE output buffers. When the Latch Enable (LE)
input is HIGH, data on the D
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes.
When LE is LOW the latches store the information that
was present on the D inputs, a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the
buffers are in the high impedance mode, but, this does
not interfere with entering new data into the latches.
n
inputs enters the latches.
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