74LCX16841MTDX Fairchild Semiconductor, 74LCX16841MTDX Datasheet

74LCX16841MTDX

Manufacturer Part Number

74LCX16841MTDX

Description

IC LATCH TRANSP 20BIT LV 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74LCXr

Datasheet

1.74LCX16841MTDX.pdf (8 pages)

Specifications of 74LCX16841MTDX

Logic Type

D-Type Transparent Latch

Circuit

10:10

Output Type

Tri-State

Voltage - Supply

2 V ~ 3.6 V

Independent Circuits

Delay Time - Propagation

1.5ns

Current - Output High, Low

24mA, 24mA

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

74LCX16841MTDX

Manufacturer:

FAIRCHILD

Quantity:

607

Company:

Meier Automation Equipment Co., Limited

Part Number:

74LCX16841MTDX

Manufacturer:

FAIRCHILD/仙童

Quantity:

20 000

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74LCX16841MEA

74LCX16841MTD

74LCX16841

Low Voltage 20-Bit Transparent Latch

with 5V Tolerant Inputs and Outputs

General Description

The LCX16841 contains twenty non-inverting latches with

3-STATE outputs and is intended for bus oriented applica-

tions. The device is byte controlled. The flip-flops appear

transparent to the data when the Latch Enable (LE) is

HIGH. When LE is LOW, the data that meets the setup time

is latched. Data appears on the bus when the Output

Enable (OE) is LOW. When OE is HIGH, the outputs are in

a high impedance state.

The LCX16841 is designed for low voltage (2.5V or 3.3V)

environment.

The LCX16841 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Order Number

applications with capability of interfacing to a 5V signal

Package Number

MS56A

MTD56

Pin Names

–D

–O

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS012578

Output Enable Input (Active LOW)

Latch Enable Input

Inputs

Outputs

Features

Note 1: To ensure the high-impedance state during power up or down, OE

should be tied to V

resistor is determined by the current-sourcing capability of the driver.

Description

5V tolerant inputs and outputs

2.3V–3.6V V

5.5 ns t

Power down high impedance inputs and outputs

Supports live insertion/withdrawal (Note 1)

Implements patented noise/EMI reduction circuitry

Latch-up performance exceeds 500 mA

ESD performance:

24 mA output drive (V

Human body model

Machine model

Package Description

max (V

through a pull-up resistor: the minimum value or the

specifications provided

200V

3.3V), 20 A I

2000V

3.0V)

October 1995

Revised April 2001

www.fairchildsemi.com

max

Related parts for 74LCX16841MTDX

74LCX16841MTDX Summary of contents

Page 1

... Logic Symbol Pin Descriptions Pin Names – – © 2001 Fairchild Semiconductor Corporation Features 5V tolerant inputs and outputs 2.3V–3.6V V specifications provided CC 5 max (V 3.3V Power down high impedance inputs and outputs Supports live insertion/withdrawal (Note output drive (V CC Implements patented noise/EMI reduction circuitry ...

Page 2

Connection Diagram Functional Description The LCX16841 contains twenty D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 20-bit operation. ...

Page 3

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 4

DC Electrical Characteristics Symbol Parameter I Quiescent Supply Current CC I Increase in I per Input CC CC Note 5: Outputs disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL PLH n ...

Page 5

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C t PLH t PZL t PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input Characteristics; ...

Page 6

Schematic Diagram Generic for LCX Family www.fairchildsemi.com 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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