SCAN18373TSSC Fairchild Semiconductor, SCAN18373TSSC Datasheet - Page 4

• Manufacturer Part Number: SCAN18373TSSC
• Description: TRANSPARENT LATCH 9-BIT 56-SSOP
• Manufacturer: Fairchild Semiconductor
• Series: SCANr

Specifications of SCAN18373TSSC

• Logic Type: D-Type Transparent Latch
• Circuit: 9:9
• Output Type: Tri-State
• Voltage - Supply: 4.5 V ~ 5.5 V
• Independent Circuits: 2
• Delay Time - Propagation: 2.5ns
• Current - Output High, Low: 24mA, 48mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their loca-
tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys-
tem data.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti-
vate their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
Bypass Register Scan Chain Definition Logic 0
Scan Cell TYPE1
Scan Cell TYPE2
4
to the SCAN18373T device. SCAN CMOS Test Access
Logic devices do not include the IEEE 1149.1 optional
identification register. Therefore, this unique captured
value can be used as a “pseudo ID” code to confirm that
the correct device is placed in the appropriate location in
the boundary scan chain.
00000000
10000001
10000010
00000011
All Others
Instruction Register Scan Chain Definition
Instruction Code
MSB
LSB
SAMPLE/PRELOAD
Instruction
EXTEST
BYPASS
CLAMP
HIGHZ