74VCX16838MTDX Fairchild Semiconductor, 74VCX16838MTDX Datasheet
74VCX16838MTDX
Manufacturer Part Number
74VCX16838MTDX
Description
IC REGISTER/BUFFER 16BIT 48TSSOP
Manufacturer
Fairchild Semiconductor
Series
74VCXr
Datasheet
1.74VCX16838MTDX.pdf
(7 pages)
Specifications of 74VCX16838MTDX
Logic Type
Shift Register
Output Type
Standard
Number Of Elements
1
Number Of Bits Per Element
16
Function
Universal
Voltage - Supply
1.65 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2005 Fairchild Semiconductor Corporation
74VCX16838MTD
74VCX16838
Low Voltage 16-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16838 contains sixteen non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig-
nals. The device operates in a 16-bit word wide mode. All
outputs can be placed into 3-State through use of the OE
Pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74VCX16838 is designed for low voltage (1.65V to
3.6V) V
The 74VCX16838 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
CC
applications with I/O compatibility up to 3.6V.
Package Number
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500034
Features
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
value of the resistor is determined by the current-sourcing capability of the
driver.
Pin Descriptions
Pin Names
OE
I
O
CLK
REGE
0
Compatible with PC100 and PC133 DIMM module
specifications
1.65V–3.6V V
3.6V tolerant inputs and outputs
t
Power-off high impedance inputs and outputs
Supports live insertion and withdrawal (Note 1)
Static Drive (I
Uses patented noise/EMI reduction circuitry
Ideal for SDRAM DIMM modules
Latch-up performance exceeds 300 mA
ESD performance:
–I
0
PD
–O
15
3.0 ns max for 3.0V to 3.6V V
4.0 ns max for 2.3V to 2.7V V
8.0 ns max for 1.65V to 1.95V V
r
r
r
Human body model
Machine model
24 mA @ 3.0V V
18 mA @ 2.3V V
6 mA @ 1.65V V
(CLK to O
15
Package Description
OH
CC
n
)
Output Enable Input (Active LOW)
Inputs
Outputs
Clock Input
Register Enable Input
/I
supply operation
OL
!
)
200V
CC
CC
CC
CC
!
2000V
through a pull-up resistor; the minimum
July 1997
Revised June 2005
Description
CC
CC
CC
www.fairchildsemi.com
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74VCX16838MTDX Summary of contents
Page 1
... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2005 Fairchild Semiconductor Corporation Features Compatible with PC100 and PC133 DIMM module specifications 1.65V– ...
Page 2
Connection Diagram Logic Diagram www.fairchildsemi.com Truth Table Inputs I CLK REGE Logic HIGH L Logic LOW X ...
Page 3
Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 3) 0. Input Diode Current ( ...
Page 4
DC Electrical Characteristics (2. Symbol Parameter V HIGH Level Input Voltage IH V LOW Level Input Voltage IL V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output ...
Page 5
AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX Propagation Delay PHL PLH n n (REGE Propagation Delay CLK to O PHL PLH n (REGE ...
Page 6
AC Loading and Waveforms TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage ...
Page 7
Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...