AM29PDL129H AMD [Advanced Micro Devices], AM29PDL129H Datasheet - Page 3

• Manufacturer Part Number: AM29PDL129H
• Description: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO
• Manufacturer: AMD [Advanced Micro Devices]

Am29PDL129H
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode
Simultaneous Read/Write Flash Memory with Enhanced
VersatileIO
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■ 128 Mbit Page Mode device
■ Dual Chip Enable inputs
■ Single power supply operation
■ Simultaneous Read/Write Operation
■ FlexBank Architecture
■ Enhanced VersatileI/O
■ SecSi
■ Both top and bottom boot blocks in one device
■ Manufactured on 0.13 µm process technology
■ 20-year data retention at 125°C
■ Minimum 1 million erase cycle guarantee per sector
PERFORMANCE CHARACTERISTICS
■ High Performance
■ Power consumption (typical values at 10 MHz)
This product has been retired and is not available for designs. For new and current designs, S29PL129J supersedes Am29PDL129H and is the factory-recom-
mended migration path. Please refer to the S29PL129J datasheet for specifications and ordering information. Availability of this document is retained for reference
and historical purposes only.
— Page size of 8 words: Fast page read access from random
— Two CE# inputs control selection of each half of the memory
— Full Voltage range: 2.7 to 3.6 volt read, erase, and program
— Data can be continuously read from one bank while
— Zero latency switching from write to read operations
— 4 separate banks, with up to two simultaneous operations
— Bank 1A: 48 Mbit (32 Kw x 96)
— Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank 2B: 48 Mbit (32 Kw x 96)
— Output voltage generated and input voltages tolerated on all
— V
— Up to 128 words accessible through a command sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
locations within the page
space
operations for battery-powered applications
executing erase/program functions in another bank
per device
control inputs and I/Os is determined by the voltage on the
V
IO
IO
TM
options at 1.8 V and 3 V I/O
pin
(Secured Silicon) Sector region
TM
Control and Dual Chip Enable Inputs
TM
(V
IO
) Control
SOFTWARE FEATURES
■ Software command-set compatible with JEDEC 42.4
■ CFI (Common Flash Interface) complaint
■ Erase Suspend / Erase Resume
■ Unlock Bypass Program command
HARDWARE FEATURES
■ Ready/Busy# pin (RY/BY#)
■ Hardware reset pin (RESET#)
■ WP#/ACC (Write Protect/Acceleration) input
■ Persistent Sector Protection
■ Password Sector Protection
■ Package options
— 45 mA active read current
— 15 mA program/erase current
— 1 µA typical standby mode current
standard
— Backward compatible with Am29F and Am29LV families
— Provides device-specific information to the system, allowing
— Suspends an erase operation to allow read or program
— Reduces overall programming time when issuing multiple
— Provides a hardware method of detecting program or erase
— Hardware method to reset the device to reading array data
— At V
— At V
— At V
— A command sector protection method to lock combinations
— Sectors can be locked and unlocked in-system at V
— A sophisticated sector protection method to lock
— 80-ball Fine-pitch BGA
— Multi Chip Packages (MCP)
host software to easily reconfigure for different Flash devices
operations in other sectors of same bank
program command sequences
cycle completion
word sectors.
setting
of individual sectors and sector groups to prevent program or
erase operations within that sector
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
IL
IH
HH
, hardware level protection for the first and last two 4K
, allows removal of sector protection
, provides accelerated programming in a factory
Publication Number: 26842
Issue Date: November 2, 2005
Rev: B Amendment/ +3
CC
level