AM29PDL129H AMD [Advanced Micro Devices], AM29PDL129H Datasheet - Page 5

• Manufacturer Part Number: AM29PDL129H
• Description: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO
• Manufacturer: AMD [Advanced Micro Devices]

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Simultaneous Operation Block Diagram . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Common Flash Memory Interface (CFI) . . . . . . . 24
Command Definitions . . . . . . . . . . . . . . . . . . . . . 27
November 2, 2005
Random Read (Non-Page Read) ........................................... 10
Page Mode Read .................................................................... 10
Simultaneous Operation ......................................................... 10
Write Protect (WP#) ................................................................ 21
Persistent Protection Bit Lock ................................................. 21
High Voltage Sector Protection .............................................. 21
Temporary Sector Unprotect .................................................. 21
Flash Memory Region ............................................................ 21
Factory-Locked Area (64 words) ............................................ 21
Customer-Lockable Area (64 words) ...................................... 22
SecSi Sector Protection Bits ................................................... 24
Enter /Exit Command Sequence ............................................ 27
Table 1. Am29PDL129H Device Bus Operations ...........................10
Table 2. Page Select .......................................................................10
Table 3. Bank Select .......................................................................11
Table 4. Am29PDL129H Sector Architecture ..................................12
Table 5. Addresses .......................................................................19
Table 6. Autoselect Codes (High Voltage Method) ........................19
Table 7. Am29PDL129H Boot Sector/Sector Block Addresses for
Protection/Unprotection
CE1# Control ...................................................................................20
Table 8. Am29PDL129H Boot Sector/Sector Block Addresses for
Protection/Unprotection
CE2# Control ...................................................................................20
Table 9. Sector Protection Schemes ...............................................21
Figure 1. ......................................................................................... 21
Figure 2. ......................................................................................... 21
Figure 3. SecSi Sector Protection Algorithm................................... 23
Figure 4. SecSi Sector Protect Verify.............................................. 24
Figure 5. ......................................................................................... 27
Am29PDL129H
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Erase And Programming Performance. . . . . . . . 45
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 45
BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 45
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46
PPB Lock Bit Status .............................................................. 27
CE1#/CE2# Timing ................................................................. 33
Read-Only Operations ........................................................... 33
Hardware Reset (RESET#) .................................................... 35
Erase and Program Operations .............................................. 36
Temporary Sector Unprotect .................................................. 41
Alternate CE# Controlled Erase and Program Operations ..... 43
Table 14. Memory Array Command Definitions ............................. 28
Table 15. Sector Protection Command Definitions ........................ 29
Figure 6. Maximum Negative Overshoot Waveform ...................... 30
Figure 7. Maximum Positive Overshoot Waveform........................ 30
Figure 8. Test Setup, VIO = 2.7 – 3.6 V........................................ 32
Figure 9. Input Waveforms and Measurement Levels ................... 32
Figure 10. Timing Diagram for Alternating Between CE1# and CE2#
Control............................................................................................ 33
Figure 11. Read Operation Timings ............................................... 34
Figure 12. Page Read Operation Timings...................................... 34
Figure 13. Reset Timings ............................................................... 35
Figure 14. Program Operation Timings.......................................... 37
Figure 15. Accelerated Program Timing Diagram.......................... 37
Figure 16. Chip/Sector Erase Operation Timings .......................... 38
Figure 17. Back-to-back Read/Write Cycle Timings ...................... 39
Figure 18. Data# Polling Timings (During Embedded Algorithms). 39
Figure 19. Toggle Bit Timings (During Embedded Algorithms)...... 40
Figure 20. DQ2 vs. DQ6................................................................. 40
Figure 21. Temporary Sector Unprotect Timing Diagram .............. 41
Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram
42
Figure 23. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 44
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