ZL50011/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50011/GDC Datasheet
ZL50011/GDC
Related parts for ZL50011/GDC
ZL50011/GDC Summary of contents
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... France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. Flexible 512 Channel DX with on-chip ZL50011/QCC ZL50011/GDC • Per-stream output channel and output bit delay programming with fractional bit advancement • ...
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Applications • Small and medium digital switching platforms • Access Servers • Time Division Multiplexers • Computer Telephony Integration • Digital Loop Carriers Description The device has 16 ST-BUS inputs (STi0-15) and 16 ST-BUS outputs (STo0-15 non-blocking ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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JTAG Support ...
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Figure 1 - ZL50011 Functional Block Diagram ...
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Figure 46 - Output Driver Enable (ODE ...
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Table 1 - FPi and CKi Input Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Changes Summary The following table captures the changes from the July 2004 issue. Page Item 12, 34, 40 (1) Pin Description - Signal XTALi (2) 2.9.3 “DPLL Bypass Mode“ (3) 3.0 “Oscillator Requirements“ 18 2.1.4 “Improved Input Jitter Tolerance with ...
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NC 122 NC 123 A2 124 A3 125 A4 126 VSS 127 VDD 128 A5 129 A6 130 A7 131 A8 132 A9 133 A10 134 A11 135 VSS 136 VDD 137 STi0 138 STi1 139 STi2 140 STi3 ...
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PINOUT DIAGRAM: (as viewed through top of package) A1 corner identified by metallized marking, mould indent, ink dot or right-angled corner 1 A ODE B CKo2 C STo2 D STo3 E STo5 F STo6 G STOHZ 6 H STo9 J ...
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Pin Description LQFP Pin LBGA Ball Number Number 10, 23, 33, D5, D6, D7 43, 48, 58, E9 68, 78, 92, F4, F9 102, 113, G4 127, 136, H4 146, 156 J6, J7 18, 21, D4, D9 32, ...
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Pin Description (continued) LQFP Pin LBGA Ball Number Number C10 14 A6, A5, B6, B5 ...
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Pin Description (continued) LQFP Pin LBGA Ball Number Number D2, C2, C1 E2, E1, F1 H3, H1, ...
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Pin Description (continued) LQFP Pin LBGA Ball Number Number C3, D3, E4 F3, G3, G1 J3, K1, L1, J2 STOHZ 12 -15 M2, K4, M3, K2 ...
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Pin Description (continued) LQFP Pin LBGA Ball Number Number 157 D11 158 C11 1, 2, 29 82, 119 - 122, 159, 160 ZL50011 Name RESET Device Reset (5 V Tolerant Input): This input ...
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Device Overview The device uses the ST-BUS input frame pulse and the ST-BUS input clock to define the input frame boundary and timing for the ST-BUS input streams with various data rates (2.048 Mbps, 4.096 Mbps and/or 8.192 Mbps). ...
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Users have to program the CKIN2 - 0 bits in the Control Register (CR), for the width of the frame pulse low cycle and the frequency of the input clock. See Table 1 for the programming of the CKIN0, CKIN1 ...
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ST-BUS Input Timing When the negative input frame pulse and negative input clock formats are used, the input frame boundary is defined by the falling edge of the CKi input clock while the FPi is low. When the input ...
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ST-BUS Output Data Rate and Output Timing The device has 16 ST-BUS serial data outputs. Any of the 16 outputs can be programmed to deliver different data rates at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps. 2.2.1 ST-BUS Output ...
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The device also delivers positive or negative output frame pulse and ST-BUS output clock formats via the programming of the FP0P, FP1P, FP2P, CK0P, CK1P and CK2P bits in the Internal Mode Selection (IMS) register. By default, the device delivers ...
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FPo2 FP2P = 0 FPo2 FP2P = 1 CKo2 (32.768 MHz) CK2P = 0 CKo2 (32.768 MHz) CK2P = 1 Figure 12 - FPo2 and CKo2 Output Timing when the CKFP2 Bit = 0 FPo2 FP2P = 0 FPo2 FP2P ...
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ST-BUS Output Timing By default, the output frame boundary is defined by the falling edge of the CKo0, CKo1 or CKo2 output clock while the FPo0, FPo1 or FPo2 output frame pulse goes low respectively. When the output data ...
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Serial Data Input Delay and Serial Data Output Offset Various registers are provided to adjust the input and output delays for every input and every output data stream. The input and output channel delay can vary from 0 to ...
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Fractional Input Bit Delay Programming In addition to the input bit delay feature, the device allows users to change the sampling point of the input bit. By default, the sampling point is at 3/4 bit. Users can change the ...
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Output Bit Delay Programming This feature is used to delay the output data bit of individual output streams with respect to the output frame boundary. Each output stream can have its own bit delay value. By default, all output ...
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External High Impedance Control, STOHZ The STOHZ outputs are provided to control the external tristate ST-BUS drivers for per-channel high impedance operations. The STOHZ outputs are sent out in 32 128 ...
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Data Delay Through The Switching Paths To maintain the channel integrity in the constant delay mode, the usage of the input channel delay and output channel delay modes affect the data delay through various switching paths due to additional ...
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By default, when the input channel delay and output channel delay are set to zero, the data throughput delay (T) is frames + (m-n). Figure 21 shows the throughput delay when the input Ch0 is switched to ...
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When the input channel delay and the output channel delay are enabled, the data throughput delay is frames - α + β + (m-n). Figure 24 shows the data throughput delay when the input Ch0 is switched ...
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Memory block programming procedure: (Assumption: The MBPE and MBPS bits are both low at the start of the procedure) • Program Bit (BPD0 to BPD2) in the IMS (Internal Mode Selection) register. • Set the Memory Block ...
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BER Count Register (BCR) - Contains the number of counted errors. When the error count reaches Hex FFFF, the bit error counter will stop so that it will not overflow. Consequently the BER Count Register will also stop at ...
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STIN#QEN2 1 0 Table 12 - Quadrant Frame 2 LSB Replacement STIN#QEN3 1 0 Table 13 - Quadrant Frame 3 LSB Replacement 2.8 Microprocessor Port The device supports the non-multiplexed microprocessor. The microprocessor port consists of a 16-bit parallel data ...
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Table 14 shows the three operating modes of the DPLL. The DPLL is controlled by the DOM (DPLL Operation Mode) register and bit 14 of the Control Register (CR). The DPLL’s status is reported in the DPLL House Keeping Register ...
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DPLL Bypass Mode DPLL Bypass mode is selected by setting high bit 14 of the Control Register (CR), as shown in Table 14. The DPLL is completely bypassed and the APLL takes its input from CKi instead of the ...
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Skew Control Circuit reference input SKEW_CONTROL The Skew Control circuit delays the selected reference input with an 8 tap tapped delay line (see Figure 26). The nominal delay between taps is 1.9 ns. Thus the selected reference can be ...
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Phase-Locked Loop (PLL) Circuit As shown in Figure 27, the PLL circuit consists of a Phase Detector, Phase Offset Adder, Phase Slope Limiter, Loop Filter, Digitally Controlled Oscillator, Divider and Frequency Select Mux. PHASE_OFFSET REF Phase Detector FEEDBACK FREERUN ...
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Divider - The Divider divides down the DCO output frequency. The following signals are generated: • C2M (a 2.048 MHz clock) • C1M5 (a 1.544 MHz clock) • FRAME (an 8 kHz frame pulse) One of these signals is selected ...
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The DPLL’s jitter transfer characteristic is determined by the internal 1.52 Hz low pass Loop Filter and the Phase Slope Limiter. The DPLL is a second order, Type 2 PLL. Figure 28 on page 38 shows the DPLL jitter transfer ...
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Figure 29 - Detailed DPLL Jitter Transfer Function Diagram (Wander Transfer Diagram) 2.11.5 Locking Range The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to maintain the synchronization. The ...
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Although a short phase lock time is desirable not always achievable due to other synchronizer requirements. For instance, better jitter transfer performance is obtained with a lower frequency loop filter which increases lock time; and better (smaller) phase ...
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The accuracy of a crystal oscillator circuit depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20 MHz crystal specified with load capacitance, each 1 pF change in load capacitance contributes ...
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Device Reset and Initialization The RESET pin is used to reset the device. When the pin is low, it synchronously puts the device in its reset state. It disables the STo0 - 15 outputs, drives the STOHZ 0 - ...
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Instruction Register The ZL50011 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in ...
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Register Address Mapping External Address A11 - A0 000 H 001 H 010 H 011 H 012 H 030 H 031 H 032 H 100 H 101 H 102 H 103 H 104 H 105 H 106 H 107 ...
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ZL50011 External CPU Address Access A11 - A0 Stream11 Input Delay Register, SIDR11 117 R/W H 118 R/W Stream12 Input Control Register, SICR12 H Stream12 Input Delay Register, SIDR12 119 R/W H Stream13 Input Control Register, SICR13 11A R/W H ...
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ZL50011 External CPU Address Access A11 - A0 Stream11 Output Delay Register, SOOR11 217 R/W H 218 R/W Stream12 Output Control Register, SOCR12 H Stream12 Output Delay Register, SOOR12 219 R/W H Stream13 Output Control Register, SOCR13 21A R/W H ...
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Detail Register Description External Read/Write Address: 000 Reset Value: 0000 FBD SLV FBD CKIN CKIN MODE Bit Name 15 FBD- Frame Boundary Determination Mode Select. When either the FBDEN or ...
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External Read/Write Address: 000 Reset Value: 0000 FBD SLV FBD CKIN CKIN MODE Bit Name 6 CBER Bit Error Rate Counter Clear: When this bit is high, it resets the internal ...
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External Read/Write Address: 001 H Reset Value: 0000 CKINP Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 11 CKINP ST ...
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External Read/Write Address: 001 H Reset Value: 0000 CKINP Bit Name 0 MBPS Memory Block Programming Start: A zero to one transition of this bit starts the memory block programming ...
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External Read/Write Address: 011 H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero ...
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External Read/Write Address: 030 H Internal Read/Write Address: 00030 Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to ...
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External Read/Write Address: 031 H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 9 ...
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External Read/Write Address: 100 Reset Value: 0000 SICR0 SICR1 SICR2 SICR3 SICR4 SICR5 0 0 ...
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External Read/Write Address: 100 Reset Value: 0000 SICR0 SICR1 SICR2 SICR3 SICR4 SICR5 0 0 ...
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External Read/Write Address: 110 Reset Value: 0000 SICR8 SICR9 SICR10 SICR11 SICR12 SICR13 0 0 ...
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External Read/Write Address: 110 Reset Value: 0000 SICR8 SICR9 SICR10 SICR11 SICR12 SICR13 0 0 ...
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External Read/Write Address: 101 Reset Value: 0000 SIDR0 SIDR1 SIDR2 SIDR3 SIDR4 SIDR5 0 0 ...
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External Read/Write Address: 111 Reset Value: 0000 SIDR8 SIDR9 SIDR10 SIDR11 SIDR12 0 0 ...
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External Read/Write Address: 200 Reset Value: 0000 SOCR0 SOCR1 SOCR2 SOCR3 SOCR4 SOCR5 0 0 ...
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External Read/Write Address: 210 Reset Value: 0000 SOCR8 SOCR9 SOCR10 SOCR11 SOCR12 0 0 ...
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External Read/Write Address: 201 Reset Value: 0000 SOOR0 SOOR1 SOOR2 SOOR3 SOOR4 SOOR5 0 0 ...
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External Read/Write Address: 211 Reset Value: 0000 SOOR8 STO8C SOOR9 STO9C SOOR10 STO10 CD6 SOOR11 STO11 CD6 SOOR12 0 ...
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Memory Address Mappings When A11 is high, the data or the connection memory can be accessed by the microprocessor port. The Bit 0 to Bit 2 in the control register determine the access to the data or connection memory ...
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Connection Memory Bit Assignment When the CMM bit (Bit0) is zero, the connection is in normal switching mode. When the CMM bit is one, the connection memory is in special transmission mode SSA3 SSA2 SSA1 Bit ...
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Absolute Maximum Ratings* Parameter 1 I/O Supply Voltage 2 Input Voltage 3 Input Voltage (5 V tolerant inputs) 4 Continuous Current at digital outputs 5 Package power dissipation 6 Storage temperature * Exceeding these values may cause permanent damage. Functional ...
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AC Electrical Characteristics Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated. AC Electrical Characteristics Characteristic 1 FPi Input Frame Pulse Width 2 FPi Input ...
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FPi CKi Input Frame Boundary Figure 32 - Frame Pulse Input and Clock Input Timing Diagram AC Electrical Characteristics Variation Characteristic CKi Input Clock cycle-to-cycle variation 1 † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures ...
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AC Electrical Characteristics Cycle-to-cycle Variation Characteristic FPi Input Frame Pulse cycle-to-cycle variation 1 † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25° 3.3 V and are for design aid only: not ...
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AC Electrical Characteristics Characteristic 1 C20i Input Clock Period 2 C20i Input Clock High Time 3 C20i Input Clock Low Time C20i Input Rise/Fall Time 4 † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are ...
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AC Electrical Characteristics - Reference Input Timing Characteristic 1 REF Period 2 REF High Time 3 REF Low Time 4 REF Rise/Fall Time 5 REF Period 6 REF High Time 7 REF Low Time 8 REF Rise/Fall Time 9 REF ...
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AC Electrical Characteristics - Input and Output Frame Boundary Alignment Characteristic 1 Input and Output Frame Offset in DPLL Master Mode 2 Input and Output Frame Offset in DPLL Bypass Mode FPi CKi (16.384MHz) FPi CKi (8.192MHz) FPi CKi (4.096MHz) ...
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AC Electrical Characteristics Characteristic 1 FPo0 Output Pulse Width 2 FPo0 Output Delay from the CKo0 falling edge to the output frame boundary 3 FPo0 Output Delay from the output frame boundary to the CKo0 Rising edge 4 CKo0 Output ...
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AC Electrical Characteristics Characteristic 1 FPo1 Output Pulse Width 2 FPo1 Output Delay from the CKo1 falling edge to the output frame boundary 3 FPo1 Output Delay from the output frame boundary to the CKo1 Rising edge 4 CKo1 Output ...
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AC Electrical Characteristics Characteristic 1 FPo2 Output Pulse Width 2 FPo2 Output Delay from the CKo2 falling edge to the output frame boundary 3 FPo2 Output Delay from the output frame boundary to the CKo2 Rising edge 4 CKo2 Output ...
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AC Electrical Characteristics Characteristic 1 STi Setup Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 2 STi Hold Time 2.048 Mbps 4.096 Mbps 8.192 Mbps † Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are at ...
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AC Electrical Characteristics Characteristic 1 STo Delay - Active to Active @2.048 Mbps @4.096 Mbps @8.192 Mbps † Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are 3.3 V and ...
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AC Electrical Characteristics Characteristic 1 STo Delay - Active to High-Z STo Delay - High-Z to Active 2.048 Mbps 4.096 Mbps 8.192 Mbps 2 Output Driver Enable (ODE) Delay - High-Z to Active 2.048 Mbps 4.096 Mbps 8.192 Mbps 2 ...
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics CS setup from DS falling 1 R/W setup from DS falling 2 Address setup from DS falling delay from the rising edge of DTA to the falling edge ...
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AC Electrical Characteristics Characteristic 1 TCK Clock Period 2 TCK Clock Pulse Width High 3 TCK Clock Pulse Width Low 4 TMS Set-up Time 5 TMS Hold Time 6 TDi Input Set-up Time 7 TDi Input Hold Time 8 TDo ...
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Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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Zarlink Semiconductor 2002 All rights reserved ISSUE 213834 ACN 213740 11Dec02 15Nov02 DATE APPRD. Package Code Previous package codes ...
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