ZL50011/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50011/GDC Datasheet - Page 36

• Manufacturer Part Number: ZL50011/GDC
• Description: Flexible 512 Channel DX with on-chip DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.10.4
As shown in Figure 27, the PLL circuit consists of a Phase Detector, Phase Offset Adder, Phase Slope Limiter, Loop
Filter, Digitally Controlled Oscillator, Divider and Frequency Select Mux.
Phase Detector - The Phase Detector compares the reference signal from the Skew Control circuit (REF) with the
FEEDBACK signal from the Frequency Select Mux. It provides an error signal corresponding to the phase
difference between the signals’ rising edges. This error signal is passed to the Phase Offset Adder.
Phase Offset Adder - The Phase Offset Adder adds the PHASE_OFFSET word (POS6-0 bits of the DPOA register)
to the error signal from the Phase Detector to create the final phase error. This value is passed to the Phase Slope
Limiter. The phase offset word (POS6-0) can be positive or negative. Since the PLL will stabilize to a situation
where the average Phase Offset Adder output is zero, a non-zero phase offset word will result in a static phase
offset between the input and output of the DPLL.
The phase offset word is a 7 bit 2’s complement value. If the selected input reference is 8 kHz or 2.048 MHz, the
step size of the static phase offset is 15.2 ns. The static phase offset can be set between -0.96 µs and +0.97 µs. If
the selected input reference is 1.544 MHz, the step size is 20.2 ns and the static phase offset can be set between
-1.27 µs and +1.29 µs.
The resolution of the Skew Control circuit is 1.9 ns. Its effect is additional to that of the phase offset word. Thus
using the Skew Control bits (SKC2-0 of the DPOA register) together with the phase offset word, users can set a
total static phase offset between -0.96 µs and +0.99 µs if the selected input reference is either 8 kHz or 2.048 MHz.
If the selected reference is 1.544 MHz, the total static phase offset can be between -1.27 µs and +1.30 µs.
Phase Slope Limiter - The Phase Slope Limiter receives the error signal from the Phase Offset Adder and ensures
that the DPLL output responds to all input transient conditions with an output phase slope below a preset limit. The
limit is based upon telecom standards requirements.
Loop Filter - The Loop Filter is similar to a first order low pass filter with a 1.52 Hz cutoff frequency for all 3
reference frequency selections (8 kHz, 1.544 MHz or 2.048 MHz). This filter defines the jitter transfer characteristic
of the DPLL.
Digitally Controlled Oscillator (DCO) - In Master mode, the DCO generates a high-speed digital clock output whose
frequency is modulated by the frequency offset value from the Loop Filter. The offset value represents the limited
and filtered phase error between the input reference and the DCO feedback signal. Based on the offset value the
DCO generates an output clock which is synchronized to the selected input reference. The DCO output is the
MCKTDM clock in Figure 25 on page 34 and Figure 27 on page 36. MCKTDM provides timing for the TDM
switching function, and timing for the ST-BUS outputs.
When the DPLL is in Freerun mode, the frequency offset is ignored and the DCO is free running at its preset center
frequency.
PHASE_OFFSET
REF
FREQ_MOD
FREERUN
Phase-Locked Loop (PLL) Circuit
Detector
Phase
FEEDBACK
Figure 27 - Block Diagram of the PLL Module
Phase
Offset
Adder
Zarlink Semiconductor Inc.
Limiter
Phase
Slope
ZL50011
36
Filter
Loop
Frequency
Select
DCO
MUX
Divider
C1M5
C2M
Data Sheet
MCKTDM
FRAME