ZL50011/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50011/GDC Datasheet - Page 12

• Manufacturer Part Number: ZL50011/GDC
• Description: Flexible 512 Channel DX with on-chip DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
LQFP Pin
Number
24 - 28
14, 15
12
13
16
17
19
20
22
30
31
34
11
A6, A5, B6,
LBGA Ball
Number
C9, C8
B5, C7
C10
B9
A9
D8
B8
A8
A7
B7
C4
A4
A3
CLKBYPS
NC1, NC2
V
V
ICONN1
XTALo
IC0 - 4
DD_APLL
Name
XTALi
ss_APLL
FPo0
SG1
TM1
TM2
REF
Zarlink Semiconductor Inc.
ZL50011
APLL Test Control (3.3 V Input with internal pull-down): For
normal operation, this input MUST be low.
APLL Test Pin 1: For normal operation, this input MUST be
low.
APLL Test Pin 2: For normal operation, this input MUST be
low.
No Connection: These pins MUST be left unconnected.
Ground for the APLL Circuit.
Power Supply for the on-chip Analog Phase Lock Loop
(APLL) Circuit: +3.3 V
Oscillator Clock Output (3.3 V Output). This pin is connected
to a 20 MHz crystal (see Figure 30 on page 40), or it is left
unconnected if a clock oscillator is connected to the XTALi pin
(see Figure 31 on page 41). If the device is to be used in DPLL
Bypass mode only, the crystal or clock oscillator can be
omitted, in which case this pin must be left unconnected.
Oscillator Clock Input (3.3 V Input). This pin is connected to
a 20 MHz crystal (see Figure 30 on page 40), or it is connected
to a clock oscillator (see Figure 31 on page 41).
If the device is to be used in DPLL Bypass mode only, the
crystal or clock oscillator can be omitted, but this pin should still
get a valid clock signal so that the device can be initialized. The
easiest way is to tie the CKi clock to this pin.
Test Clock Input: For device testing only, in normal operation,
this input MUST be low.
Internal connection (3.3 V Tolerant Inputs with internal
pull-down): In normal mode, these pins must be low.
Reference Input (5 V Tolerant Input): This pin accepts an
8 kHz, 1.544 MHz or 2.048 MHz timing reference. It is used as
one of the references for the DPLL in the Master mode. This
pin is ignored in the DPLL Bypass Mode.
When this pin is not in use, it is required to be driven high or
low by connecting it to Vdd or ground through an external
pull-up resistor or external pull-down resistor.
Internal Connection: In normal mode, this pin must be low.
ST-BUS Frame Pulse Output 0 (5 V Tolerance Three-state
Output): ST-BUS frame pulse output which stays low for
244 ns or 122 ns at the output frame boundary. Its frequency is
8 KHz. The polarity of this signal can be changed using the
Internal Mode Selection register.
12
Description
Data Sheet