ZL50011/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50011/GDC Datasheet - Page 38

• Manufacturer Part Number: ZL50011/GDC
• Description: Flexible 512 Channel DX with on-chip DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL50011
Data Sheet
The DPLL’s jitter transfer characteristic is determined by the internal 1.52 Hz low pass Loop Filter and the Phase
Slope Limiter. The DPLL is a second order, Type 2 PLL. Figure 28 on page 38 shows the DPLL jitter transfer
characteristic over a wide range of frequencies, while Figure 29 on page 39 expands the portion of Figure 28
around the 0 dB jitter transfer region. The jitter transfer function can be described as a low pass filter to 1.52 Hz,
-20 dB/decade, with peaking less then 0.5 dB.
2.11.4
Frequency Accuracy
Frequency accuracy is defined as the absolute tolerance of an output clock when the synchronizer is not locked to
an external reference, but is in a free running mode.
In Freerun mode, the DPLL is not synchronized to any reference. The DPLL provides output clocks and frame
pulses based on the DPLL master clock. The PLL block’s DCO circuit ignores its frequency offset input and free
runs at its center frequency. Because of the granularity of the center frequency control value, the DCO free run
frequency is -0.03 ppm off the ideal frequency. The DCO is clocked by the DPLL master clock MCKDPLL. The
APLL generates the DPLL master clock from the oscillator. Thus the DPLL free run accuracy is affected by the
oscillator accuracy. The DPLL free run accuracy is -0.03 ppm plus the accuracy of the oscillator.
Figure 28 - DPLL Jitter Transfer Function Diagram - Wide Range of Frequencies
38
Zarlink Semiconductor Inc.