ZL50011/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50011/GDC Datasheet - Page 8

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ZL50011/GDC

Manufacturer Part Number
ZL50011/GDC
Description
Flexible 512 Channel DX with on-chip DPLL
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
Changes Summary
The following table captures the changes from the July 2004 issue.
12, 34, 40
18
47
Page
(1) Pin Description - Signal XTALi
(2) 2.9.3 “DPLL Bypass Mode“
(3) 3.0 “Oscillator Requirements“
2.1.4 “Improved Input Jitter Tolerance with
Frame Boundary Determinator“
Table 16 - “Control Register (CR) Bits“ - bits
“FBDMODE“ and “FBDEN“
Item
Zarlink Semiconductor Inc.
ZL50011
8
Clarified initialization input clock requirement in
DPLL Bypass mode.
Added a new section to describe the improved
input jitter tolerance with the frame boundary
determinator.
Renamed bit 15 from Unused to FBDMODE and
added description to clarify the frame boundary
determinator operation.
Clarified FBDEN description.
Change
Data Sheet

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