AM79C930VC/W AMD [Advanced Micro Devices], AM79C930VC/W Datasheet
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AM79C930VC/W
Related parts for AM79C930VC/W
AM79C930VC/W Summary of contents
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PRELIMINARY Am79C930 PCnet™-Mobile Single-Chip Wireless LAN Media Access Controller DISTINCTIVE CHARACTERISTICS Capable of supporting the IEEE 802.11 standard (draft) Supports the Xircom Netwave™ media access control (MAC) protocols Supports MAC layer functions Individual 8-byte transmit and 15-byte receive FIFOs Integrated ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. AM79C930 DEVICE NUMBER/DESCRIPTION Am79C930 Single-Chip Wireless LAN Media Access Controller Valid ...
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BLOCK DIAGRAM PCMCIA Mode MOE MWE MA 16–0 MD 7–0 XCE SCE FCE USER6–0 A14–0 D7–0 REG CE1 OE Bus IORD Interface Unit IOWR (PCMCIA) RESET WE WAIT INPACK IREQ STSCHG PMX2–1 CLKIN TEST PWRDWN ...
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BLOCK DIAGRAM Bus Interface Unit IREQ A14–0 or LA23–17, SA16–0 D7–0 PCMCIA or ISA Control Signals CLKIN MD[7:0] MA[16:0] System Interrupt Generator Address Buffer Bus Multi- Data Buffer ...
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BLOCK DIAGRAM Transceiver Attachment Interface Unit IRQ Interrupt Generator MD[7:0] TIR0 TIR... TIR31 TAICE Slave Slave Control Control Memory Interface MA[4:0] Bus I/O DRQ[1:0] and DMA RXCSEL RXCIN DPLL RESET CLKIN ...
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AMD TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin 3: USER4/LA17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD Bus Interface Unit Interaction Transceiver Attachment Interface Unit TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD TIR10: TX FIFO Data Register TIR11: Transmit Sequence Control TIR12: Byte Count Register LSB TIR13: Byte Count Register MSB TIR14: Byte Count Limit LSB TIR15: Byte Count Limit MSB TIR16: Receiver Control TIR17: Receive Status Register TIR18: RX FIFO ...
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TCR24: RSSI Sample Start TCR25: RSSI Configuration TCR26: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD TIMING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PCMCIA CONNECTION DIAGRAM 1 USER2 USER3 2 USER4 3 VDDM 4 XCE 5 MA11 6 VSSM 7 MA9 8 MA8 9 MA13 10 MWE 11 MA14 12 MA16 13 MA15 14 MA12 15 VDDM MA7 18 ...
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PCMCIA PIN SUMMARY Listed by Pin Number Pin No. Pin Name Pin No. 1 USER2 37 2 USER3 38 3 USER4 39 4 VDDM 40 5 XCE 41 6 MA11 42 7 VSSM 43 8 MA9 44 9 MA8 45 ...
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PCMCIA PIN LIST Listed by Pin Name Pin Name Pin No. Pin Name A0 46 HFPE A1 47 INPACK A10 71 IORD A11 69 IOWR A12 56 IREQ A13 64 LFCLK A14 63 LFPE A2 49 LLOCKE A3 51 LNK ...
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PCMCIA PIN FUNCTION SUMMARY PCMCIA Pin Summary No. of Pins Pin Name 15 A14–A0 PCMCIA address bus lines 8 D7–D0 PCMCIA data bus lines 1 RESET PCMCIA bus RESET line Card Enable 1—used to enable the D7–0 pins for PCMCIA ...
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PCMCIA PIN FUNCTION SUMMARY (continued) PCMCIA Pin Summary (continued) No. of Pins Pin Name 1 TDO Test Data Out—this is the data output signal for IEEE 1149.1 testing 1 TMS Test Mode Select—this is the test mode select for IEEE ...
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PCMCIA PIN FUNCTION SUMMARY (continued) PCMCIA Pin Summary (continued) No. of Pins Pin Name 2 ADIN1–2 Comparator—A/D comparator inputs 12 V Power CC 13 GND Ground User-definable I/O pins with direct accessibility and control through TCR and 7 USER0–USER6 TIR ...
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ISA PLUG AND PLAY BLOCK DIAGRAM MOE MWE MA 16–0 MD 7–0 XCE SCE FCE LA23–17 SA126–0 SD7–0 AEN BALE Bus MEMR Interface Unit (ISA IOR Plug and Play) IOW RESET MEMW IOCHRDY IRQ(X) RFRSH PMX2–1 CLK20 TEST PWRDWN P ...
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ISA PLUG AND PLAY CONNECTION DIAGRAM 1 LA19 SA16 2 LA17 3 VDDM 4 XCE 5 MA11 6 VSSM 7 MA9 8 MA8 9 MA13 10 MWE 11 MA14 12 MA16 13 MA15 14 MA12 15 VDDM ...
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ISA PLUG AND PLAY PIN LIST Listed by Pin Number Pin No. Pin Name Pin No. 1 LA19 37 2 SA16 38 3 LA17 39 4 VDDM 40 5 XCE 41 6 MA11 42 7 VSSM 43 8 MA9 44 ...
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ISA PLUG AND PLAY PIN LIST Listed by Pin Name Pin Name Pin No. Pin Name ACT 98 MA11 ADIN1 134 MA12 ADIN2 135 MA13 ADREF 137 MA14 AEN 48 MA15 ANTSLT 132 MA16 AVDD 138 MA2 AVSS 136 MA3 ...
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ISA PLUG AND PLAY PIN SUMMARY No. of Pins Pin Name 7 LA23–LA17 ISA upper address bus lines 17 SA16–SA0 ISA lower address bus lines 8 SD7–SD0 ISA data bus lines 1 RESET RESET input Memory Read—used to enable the ...
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ISA PLUG AND PLAY PIN SUMMARY (continued) No. of Pins Pin Name 1 TXC Transmit Clock—may be configured either as input or output Low Frequency Power Enable—used to power up the low-frequency section of 1 LFPE the transceiver 1 LFCLK ...
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PIN DESCRIPTIONS Pins with Internal Pull Up or Pull Down Devices Several pins of the Am79C930 device include internal pull up or pull down devices. With the exception of the RESET pin, these pins are fully programmable as inputs or ...
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AMD The functionality of the following pins is determined, at least in part, by the connection of the PCMCIA pin: PCMCIA Mode ISA Plug and Play Mode Pin Name USER6 USER5 USER4 USER3 USER2 USER1 USER0 A[14:0] LLOCKE D[7:0] CE1 ...
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Function Mode Standby mode Common Memory Read Even Byte Common Memory Read Odd Byte Common Memory Write Even Byte Common Memory Write Odd Byte Attribute Memory Read Even Byte Attribute Memory Read Odd Byte Attribute Memory Write Even Byte Attribute ...
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AMD IOR I/O Read The IOR signal is made active by the ISA host in order to read data from the Am79C930 device’s I/O space. IOW I/O Write The IOW signal is made active by the ISA host in order ...
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Clock Pins CLKIN System Clock CLKIN is the clock input for the Am79C930 device’s logic functions. CLKIN is used to drive the CLKIN input of the embedded 80188 core. The BIU section uses the CLKOUT signal from the 80188 embedded ...
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AMD is deasserted when the RESET pin is issued or the CRC reset bit is set to 1 (SIR0); when the TXS bit is set to 1 (TIR8) or the RXS bit is set to 1 (TIR16); when TXRES bit ...
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TXMOD Transmit Modulation Enable TXMOD is an active low output that is used to enable the transmit modulation function of the attached trans- ceiver. This pin is directly controlled by the transmit state machine in the TAI and the TXMOD ...
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AMD IEEE 1149.1 Test Access Port Pins TCK Test Clock TCK is the clock input for the boundary scan test mode operation. TCK frequency may be as high as 10 MHz. TCK does not have an internal pull-up resistor and ...
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VDDT, VDDU1, VDDU2, VDDP, VCC VDDM AVDD, VDD5 5 V All Both All Both Any Combination Both and ...
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AMD for an output function. This means that there are con- figurations for which a read of the pin data register bit will not reflect what has most recently been written to the pin data register bit ( i.e., if ...
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Note that a read of the USERDT[0] bit (TIR29[0]) will al- ways give the current USER0/RFRSH pin value, regard- less of pin configuration setting. PCMCIA USER1EN Pin TCR14[ ...
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AMD Pin 94: RXC/IRQ10/EXTA2DST The RXC/IRQ10 pin may be configured for input opera- tion, output operation, ISA IRQ10 operation, and as an output providing the RX clock information (whether de- rived from the RXDATA stream through Am79C930 device DPLL operation ...
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ENXCHBSY bit of TCR28 and the CHBSYU bit of TIR5 and operates independently of the bits in the table below. In addition to the functionality listed above, the USER5/IRQ4/EXTCHBSY pin may be used as the source for CCA information, instead ...
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AMD Pin 101: SDCLK The SDCLK pin may be configured for input or output operation. The output drive may be programmed for reg- ister-driven or auto-pulse generation. The auto-pulse may be programmed for either active low or active high SDCLKEN ...
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Pin 115: TXC The TXC pin may be configured for input or output op- eration according to the table below: TXC input configuration is the reset default configura- tion. This configuration allows an external transceiver to control the clock that ...
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AMD Pin 126: TXCMD The TXCMD pin may be configured to drive a trans- ceiver control reference signal, using one of two timing RCEN TIR11[ Transmit state machine generated signals T1, T2, T3, TXP _ ON and O_TX ...
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PCMCIA mode. Pin functionality is programmed according to the follow- ing table: PCMCIA ANTSEN ANSLTLFN Pin Value TIR26[3] TCR30[ Pin 142: TXCMD/LA21 The TXCMD/LA21 ...
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AMD PCMCIA LLOCKEN Pin Value TCR14[ FUNCTIONAL DESCRIPTION Basic Functions System Bus Interface Function The Am79C930 device is designed with a choice of two system bus interfaces. The system designer may choose between the ...
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PCMCIA Interface — The Am79C930 device fully sup- ports the PCMCIA standard, revision 2.1. The PCMCIA interface on the Am79C930 device sup- ports both memory and I/O cycles. The data bus is 8 bits in width. The address bus is ...
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AMD ISA (IEEE P996) Plug and Play Interface — The Am79C930 device fully supports the ISA Plug and Play specification, revision 1.0a. The ISA Plug and Play interface on the Am79C930 de- vice supports both memory and I/O cycles. The ...
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Memory Interface The memory interface is provided to support direct con- nection of both a non-volatile memory (typically Flash memory) and an SRAM and an additional peripheral de- vice. Separate chip enables for Flash, SRAM, and an extra peripheral device ...
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AMD the media is considered busy and the MAC should defer to the existing message. This function is implemented in hardware in the TAI Unit. Additionally, each station is required to implement a Net Allocation Vector (NAV) in order to ...
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T1 and T2 cycles of the 80188 access. The Memory Ad- dress Bus is internally shared between the 80188 core and the BIU. This bus also attaches to the Transceiver Attachment ...
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AMD Transceiver Attachment Interface Unit The TAI Unit includes the following subfunctions: TAI register set TX FIFO TX data serialization TX CRC32 generation TX CRC8 generation TX status reporting RX preamble and Start of Frame detection RX data deserialization RX ...
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TXS 4 X TSCLK O_TX TXP_ON TX default bit TXDATA TSCLK = TCLKIN when CLKGT20 = 0 TBCLK = TSCLK X 20 The values HDR, DRB, TGAP1, TGAP2, TGAP3, and TGAP4 are programmable values that are stored ...
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AMD Transceiver-Based TX Power Ramp Control — The CTS signal may be used to synchronize operations be- tween the Am79C930 device and transceivers that wish to perform their own transmit timing sequence. When the CTS signal is enabled by setting ...
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These register values can be used to determine the end of a received frame. When good CRC values are found, these may be sig- naled to the 80188 core through interrupt bits in TIR5. ...
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AMD register of TCR4. ADIN2 becomes active after ADIN1 by the amount of delay specified in the RSSI Sample Start time of TCR24. ADIN2 remains active for the time pro- grammed in the A2DT register (TCR25). The converter output should ...
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CLKIN period when the CLKGT20 bit of MIR9 is set to 1. (For data rate with CLKIN = 20 MHz and CLKGT20 = 0, resolution is 50 ns.) After each pair ...
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AMD UBDCS URSSI TCR28:1 TCR28 The current CCA result is reported in the CHBSY bit of TIR26. A rising edge of CHBSY ...
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Diversity decision logic for determining if a satisfactory antenna has been found. These inputs to the Stop Di- versity decision logic are enabled by specific bits of TCR28. The UBDSD bit of TCR28 is used to select/ deselect the Baud ...
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AMD The following is a brief summary of the IEEE 1149.1 compatible test functions implemented Am79C930 device: Boundary Scan Circuit The boundary scan test circuit uses five pins: TRST, TCK, TMS, TDI, and TDO. These five pins are collec- tively ...
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Power Down bit (bit 2) of the PCMCIA Card Configura- tion and Status Register. In the ISA Plug and Play mode, the host requests a power down by writing ...
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AMD Writing the Power Down bit of the ISA Power Down bit of SIR3 will cause a request for a power down to be generated to the 80188 core via an interrupt bit in MIR0. The decision ...
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Am79C930 Device PCMCIA Mode Resource Requirements Common Common Memory Range Memory Size 0000h – 7FFFh 32 Kbytes OR 0 bytes The I/O range is adjusted through bit 2 (EIOW = Expand I/O Window) of SIR1 = Bank Switching Select register). ...
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AMD Some of the Am79C930 device’s PCMCIA Common Memory locations have predefined uses and, therefore, are not freely available to the device driver. Am79C930 Device PCMCIA Mode Common Memory Restricted Space PCMCIA Address in Common Memory SIR1[5:3] 0000h – 03FFh ...
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The SRAM is intended to serve as a shared memory re- source between the driver operating through the system interface and the 80188 core operating through the Am79C930 memory interface bus. Even though SRAM memory locations 0 0400h through 0 ...
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AMD Am79C930 Device PCMCIA Mode Attribute Memory Restricted Space PCMCIA Address in Attribute Memory SIR1[5:3] Size of Restricted Space 7FE0h – 7FFFh 111 32 bytes of Attribute memory, 16 bytes of actual Flash memory space PCMCIA I/O Resources — The ...
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The following table indicates the mapping of all I/O re- sources that are accessible through the Am79C930 PCMCIA system interface. Note that some resources Am79C930 Device PCMCIA Mode I/O MAP Resource Resource Name Mnemonic SIR0: General SIR0: GCR Configuration Register ...
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AMD Am79C930 Device ISA Plug And Play Mode Memory And I/O Resource Requirements Memory Range Memory Size MBA*+0000h – 32 Kbytes MBA*+7FFFh OR 0 bytes *MBA = ISA Plug and Play Memory Base Address **IOBA = ISA Plug and Play ...
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This alignment requirement should be in- cluded in the Resource Data that is programmed into the Flash device and read by the Plug and Play configura- tion ...
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AMD The SRAM is intended to serve as a shared memory re- source between the driver operating through the system interface and the 80188 core operating through the Am79C930 memory interface bus. Even though SRAM memory locations 0 0400h through ...
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Am79C930 Device ISA Plug And Play Mode I/O MAP Resource Name Mnemonic SIR0: General SIR0: GCR Configuration Register SIR1: Bank Switching SIR1: BSS Select Register SIR2: Local Memory SIR2: LMAL Address [7:0] SIR3: Local Memory SIR3: LMAU Address [14:8] SIR4: ...
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AMD ISA Plug and Play Register Set — The Am79C930 de- vice fully supports the ISA Plug and Play specification, revision 1.0a. The Am79C930 device supports the Plug and Play Auto-configuration scheme. The Plug and Play Am79C930 Device ISA Plug ...
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Am79C930 Device ISA Plug And Play Mode Plug And Play Register Set ISA Plug and Play Register Name Set READ_DATA port Serial Isolation Configuration Control Wake [CSN] Resource Data Status Card Select Number (CSN) Logical Device Number Unused Activate I/O ...
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AMD The Am79C930 device maps the Resource Data regis- ter accesses into 1K–16 of the upper 1 Kbytes of the Flash memory space so that Resource Data may be read from the Flash memory. Byte 0 of the Am79C930 device’s ...
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Core Memory Map Using Scheme “A”, LMCS=1FF8h, UMCS=E038h, MIR0[6]=0 80188 Address Active 80188 in Memory Chip Select LCS 0 0000h–0 03FFh LCS 0 0400h–0 041Fh LCS 0 0420h–0 042Fh LCS 0 0430h–0 043Fh LCS 0 0440h–0 047Fh LCS 0 ...
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AMD MAC (80188 core) Memory Restrictions — Some of the Am79C930 device 80188 core’s memory locations have predefined uses and, Restricted Space In The 80188 Core Memory Map Using Scheme RAS or RBS, LMCS=1FF8h, UMCS=E038h, MIR0[7]= 80188 Address ...
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TIR10 also possible to use 80188 MOV instruc- tions to unload RX data from the RX FIFO. The RX FIFO may be unloaded by reading from TIR18. DMA Channel Allocation In The 80188 Core 80188 DMA Channel ...
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AMD The sleep state machine is returned to its idle state (i.e., awake). The memory bus arbitration state machine is re- turned to its idle state. The following registers and state machines which are UNAFFECTED by assertion of the SWRESET ...
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The sleep state machine is returned to its idle state (i.e., awake). The following registers and state machines are UNAFFECTED by assertion of the PCMCIA COR SRESET bit of COR[7]: All TIR registers are unaffected by COR SRESET. All TCR ...
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AMD The MIR space contains 16 registers which are used by the firmware to control allow communication between the firmware (MAC layer) and the device driver. This register set also contains the power down registers. These registers are only accessible ...
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SIR0: General Configuration Register (GCR) This register is used to control general functions related to the Am79C930, particularly interrupts to and from the 80188 core and power down functions. Bit Name Reset Value 7 SWRESET 6 CORESET 5 DISPWDN 4 ...
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AMD 2 INT2EC 1 ENECINT 0 DAM SIR1: Bank Switching Select Register (BSS) This register contains Bank Select bits for various Am79C930 resources and other control bits. Bit Name Reset Value 7 ECATR 6 Reserved 5 FS 4:3 MBS 2 ...
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SIR2: Local Memory Address Register [7:0] (LMA) This register is the beginning address on the local bus for system interface I/O transfers that are made to the I/O Data Port. This register automatically increments by Bit Name Reset Value 7:0 ...
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AMD SIR5: I/O Data Port B (IODPB) This register is a system interface I/O address alias of I/O Data Port A. Bit Name Reset Value 7:0 IODPB[7:0] SIR6: I/O Data Port C (IODPC) This register is a system interface I/O ...
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PDC 3 SYSINT 2 INT2SYS 1 SYSINTM 0 PWDNDN MIR1: Power Up Clock Time [3:0] (PUCT) This register is used to determine the length of time that will be used to allow the CLKIN buffer circuit to power up ...
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AMD MIR3: Power Down Length Count [15:8] (PDLC) This register is used to determine the length of power down cycles. Before execution of the power down se- quence, the 80188 core must load the PDLC counter. Bit Name Reset Value ...
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MIR8: Flash Wait States This register gives the Flash Wait states. Bit Name Reset Value 7:4 Reserved 3 HOSTALLOW 2 Reserved 1:0 FLASHWAIT[1:0] MIR9: TCR Mask STSCHG Data This register contains TCR Mask, STSCHG Data, and SRAM Wait States. Bit ...
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AMD 6 Reserved 5:4 SRAMWAIT[1:0] 3 HOSTLONGWAIT 2 INITDN 1 TCR Mask 0 STSCHGD – Reserved. Must be written Reads of this bit produce undefined ...
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MIR10: Reserved This register is reserved. Bit Name Reset Value 7:0 Reserved MIR11: Reserved This register is reserved. Bit Name Reset Value 7:0 Reserved MIR12: Reserved This register is reserved. Bit Name Reset Value 7:0 Reserved MIR13: Reserved This register ...
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AMD Transceiver Attachment Interface Registers (TIR Space) The Transceiver Attachment Interface (TAI) Unit con- tains a total of 64 registers. Thirty-two of the registers are directly accessible from the 80188 embedded core and from the system interface through the BIU. ...
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TIR mapping with SIR1 bit 2 (EIOW) set to “0” = normal TIR window mode. Note that EIOW = 0 is the only setting TIR Register Number TIR Register Name 0 Network Control 1 Network Status 2 Serial Device 3 ...
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AMD TIR mapping with SIR1 bit 2 (EIOW) set to “1” = Ex- panded TIR window mode. Note that the setting TIR Register Number TIR Register Name 0 Network Control 1 Network Status 2 Serial Device 3 Fast Serial Port ...
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TIR0: Network Control General control for the transceiver device attached to the transceiver interface pins. Bit Name Reset Value 7 LNK 6 ACT 5 SRES 4 SSTRB 3 Reserved 2 RXP 1 LFPE 0 HFPE TIR1: Network Status The TAI ...
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AMD 1 RXDRQ 0 TXDRQ TIR2: Serial Device TAI Serial Device register. This register is used to con- trol the serial device interface. Bit Name Reset Value 7 Reserved 6–4 SDS[3:1] 3 SDCP 2 SDC 1 SDDT 0 SDD 90 ...
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TIR3: Fast Serial Port Control This register provides a relatively quick write access to the Serial Port signals of the device (i.e., SDCLK and SDDATA). The SDSEL3-1 signals must be previously set with an access to the Serial Port control ...
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AMD 5 MOREINT 4 TXCNT 3 TXDONE 2 CRCS 1 SDSNT 0 TXFBN TIR5: Interrupt Register The TAI Interrupt Register 2 provides interrupt status in- formation. Any interrupt bit may be cleared by writing the bit location. ...
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TIR6: Interrupt Unmask Register 1 Interrupt Unmask Register 1. Each bit in this register will unmask the corresponding interrupt of Interrupt Regis- ter 1 (TIR4) when the unmask bit is set to 1. When the Bit Name Reset Value 7 ...
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AMD TIR8: Transmit Control This register is the Transmitter Control register. Bit Name Reset Value 7 TXRES 6 TXFR 5 DMA_SEL 4 EN_TX_CRC 3 RATE_SW 2–1 TCRC[1:0] 0 TXS ...
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TIR9: Transmit Status Transmit Status register. Indicates the current status of the Transmit portion of the TAI. Writes to these bits have no effect. Bit Name Reset Value 7 TXCRC 6 TXSDD 5 Reserved 4–1 TXFC[3:0] 0 TXBSY TIR10: TX ...
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AMD TIR11: Transmit Sequence Control This register is the Transmit Sequence Control. The bits in this register determine the function of the transmit sequence signals. Bit Name Reset Value 7 RXCD 6 USER6D 5 USER5D 4 LLOCKE 3 RCEN 2 ...
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TIR12: Byte Count Register LSB This register is the Byte count register LSB. This register contains the lower 8 bits of the 12-bit byte count for receive and transmit messages. This is a working Bit Name Reset Value 7:0 BC[7:0] ...
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AMD TIR15: Byte Count Limit MSB This register is the Byte Count Limit MSB register. Bit Name Reset Value 7–4 Reserved 3–0 BCLT[11:8] TIR16: Receiver Control This register is the Receiver Control register. This regis- ter allows basic control of ...
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RXFOR 4–1 RXFC[3:0] 0 RXBSY TIR18: RX FIFO Data Register This register is the RX FIFO Data register. This register allows direct access to the RX FIFO in the TAI. When read, the RX FIFO read pointer is automatically ...
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AMD TIR21: CRC32 Correct Byte Count MSB This register is the CRC32 Correct Byte Count MSB register. Bit Name Reset Value 7–4 Reserved 3–0 C32C[11:8] TIR22: CRC8 Correct Byte Count LSB This register is the CRC8 Correct Byte Count LSB ...
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TIR24: TCR Index Register This register is the TCR Index register. This register is used as an address into indirect TAI register space. The value in the TCR Index Register is used as an address Bit Name Reset Value 7:6 ...
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AMD 2 ADDA 1 SRCS 0 STRTC TIR27: Serial Approximation Register This register is the SAR register. Contains the A/D con- verter’s Serial Approximation Register value. A read Bit Name Reset Value 7 CACT 6–0 SAR[6:0] 102 ...
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TIR28: RSSI Lower Limit This register is the RSSI Lower Limit register. The value in this register is compared against converted RSSI in- put values. When the converted RSSI value is equal to Bit Name Reset Value 7 RSALT 6–0 ...
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AMD TIR31: TEST The TAI TEST register is a reserved location. Bit Name Reset Value 7 Reserved 6–0 TC[6:0] TAI Configuration Register Space (TCR) The Transceiver Attachment Interface (TAI) Unit con- tains a total of 64 registers. Thirty-two of the ...
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TCR1: Transmit Configuration This register is the Transmit Configuration register. CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7 TXENDCB 6–5 Reserved 4 TXDI 3–2 TXDLC 1–0 TXDC SD[1:0] Start ...
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AMD TCR2: Clock Recovery This register is the Configuration register. Bit Name Reset Value CONFIGURATION REGISTER INDEX: 7 WNS2 6 CLKRS 5 ECLK 4:0 CLKP[4:0] TCR3: Receive Configuration This register is the Receive Configuration register. CONFIGURATION REGISTER INDEX: Bit Name ...
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TCR4: Antenna Diversity Timer This register is the Antenna Diversity Timer register used to control antenna dwell time during antenna diversity measurements. CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7 ANTEN 6 Reserved 5–0 ADT[5:0] TCR5: TX Ramp Up Timing ...
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AMD TCR6: TX Ramp Down Timing This register is the TX Ramp Down Timing register. This register determines the ramp down timing of the TX enable signals. CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7:4 TGAP3[3:0] 3:0 TGAP4[3:0] TCR7: Pin ...
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U1INTCNT 2 TXCMDT 1 ANTSLTLD 0 TXDATALD addition, the USER5/IRQ4 pin may be used to produce interrupts to the 80188 embedded controller. This capability is controlled by ...
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AMD TCR8: Start Delimiter LSB This register is the Start Delimiter LSB register. CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7–0 SDLT[7:0] TCR9: Start Delimiter CSB This register is the Start Delimiter CSB register. CONFIGURATION REGISTER INDEX: Bit Name Reset ...
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TCR11: Interrupt Register 3 This register is the TAI Interrupt Register 3. Provides in- terrupt status information. Any interrupt bit may be cleared by writing the bit location. Writing bit location has no ...
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AMD TCR13: Pin Configuration A This register is the Pin Configuration A register. This register is used to set the state of various pins as outputs or as high impedance inputs. CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7 LNKEN ...
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Reserved 4:0 USEREN[4:0] TCR15: Pin Configuration C This register is the Pin Configuration C register. This register is used to set the state of the ACT, STSCHG, CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7 ANTSLTLEN 6 TXDLEN 5 ...
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AMD 2 USER5EN 1 ACTEN 0 STSCHGFN TCR16: Baud Detect Start This register is the Baud Detect Start register. This reg- ister is used to program the start time for the Baud de- tection circuit. The start time is compared ...
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TCR17: Baud Detect Lower Limit This register is the Baud Detect Lower Limit register (TCR17). CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7–6 Reserved 5–0 BDLLT[5:0] TCR18: Baud Detect Upper Limit. This register is the Baud Detect Upper Limit register. ...
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AMD TCR19: Baud Detect Accept Count for Carrier Sense This register is the Baud Detect Accept Count for Carrier Sense register. When the number of positive baud de- tect test results in the baud detection circuit reaches the value in ...
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CONFIGURATION REGISTER INDEX: Bit Name Reset Value 3–0 BDRN[3:0] TCR22: Baud Detect Accept Count This register is the Baud Detect Accept Count register. A read-only register that indicates the current number of good transitions detected by the baud detector. CONFIGURATION ...
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AMD CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7:6 Reserved 5:0 SS[5:0] TCR25: RSSI Configuration This register is the RSSI Configuration register. This register is used to converter parameters. CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7 UXA2DST 6 ENEXT ...
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A2DT[3:0] ANTSLT CCA_TEST (Internal Signal) START_A2D (Internal Signal) CACT=TIR27[7] SAR[6:0] When ENSAR = 1 ADIN1 (when ENEXT=1) ADIN2 (when ENEXT=1) SAR_LATCH (Internal Signal period of CLKIN tA = (period of CLKIN when CLKGT20 = 1 ...
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AMD TCR26: Reserved This register is the TAI reserved location register. CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7–0 Reserved TCR27: TIP LED Scramble This register is the Network Interface Polarity register. This register is used to set the polarity ...
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TCR28: Clear Channel Assessment Configuration This register is the Clear Channel Assessment Configuration register. The bits in this register are used CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7 RXCFN 6 ENXSDF 5 ENXCHBSY 4 RUPD 3 STPEN 2 UBDSD ...
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AMD 1 UBDCS 0 URSSI TCR29: Reserved This register is a TAI reserved location. CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7–0 Reserved TCR30: Pin Function and Data Rate This register is the Pin Function and Data Rate control register. ...
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DR[2:0] TCR31: Device Revision This register is the Device Revision register. CONFIGURATION REGISTER INDEX: Bit Name Reset Value 7–0 REV[7: then a 16-bit deep serial FIFO is inserted ...
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AMD PCMCIA CCR Registers and PCMCIA CIS Space Two bytes of attribute memory space have been used by the Am79C930 device for storage of two card configuration registers. These two registers are found at attribute memory locations 800h and 802h. ...
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Interrupt 0 Reserved PCMCIA Card Information Structure (CIS) The PCMCIA CIS space has been allocated to reside in the flash memory space of a design based on the Am79C930 device. This space corresponds to 1K–16 bytes of the uppermost ...
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AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature Under Bias: Supply Voltage to AVSS or DVSS (AVDD, DVDD ...
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DC CHARACTERISTICS (continued) 5.0 V Am79C930 DC Characteristics Parameter Symbol Parameter Description IDDPD2 Power Supply Current IDDPD3 Power Supply Current CIN Input Pin Capacitance CO I/O or Output Pin Capacitance CCLK BCLK Pin Capacitance Notes OL1 = 4mA ...
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AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature Under Bias: Supply Voltage to AVSS or DVSS (AVDD, DVDD ...
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DC CHARACTERISTICS (continued) 3.3 V Am79C930 DC Characteristics Parameter Symbol Parameter Description IDDPD2 Power Supply Current IDDPD3 Power Supply Current CIN Input Pin Capacitance CO I/O or Output Pin Capacitance CCLK BCLK Pin Capacitance Notes OL1 = 2.4mA ...
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AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature Under Bias: Supply Voltage to AVSS or DVSS (AVDD, DVDD ...
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AC CHARACTERISTICS 5.0 AND 3.3 V PCMCIA INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature Under Bias: Supply Voltage to AVSS or DVSS (AVDD, DVDD ...
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AMD PCMCIA MEMORY WRITE ACCESS Parameter Symbol Parameter Description Address setup to WE tAVWL Address setup to WE tAVWH tWMAX Write recovery time (Address hold from WE CE setup to WE tELWH CE setup to WE tELWL CE hold from ...
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PCMCIA I/O READ ACCESS Parameter Symbol Parameter Description Address setup to IORD tAVIGL Address hold from IORD tIGHAX REG setup to IORD tRGLIGL REG hold from IORD tIGHRGH CE setup to IORD tELIGL CE hold from IORD tIGHEH IORD width ...
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AMD PCMCIA I/O WRITE ACCESS Parameter Symbol Parameter Description Address setup to IOWR tAVIWL Address hold from IOWR tIWHAX REG setup to IOWR tRGLIWL REG hold from IOWR tIWHRGH CE setup to IOWR tELIWL CE hold from IOWR tIWHEH IOWR ...
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AC CHARACTERISTICS 5.0 AND 3.3 V ISA INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature Under Bias: Supply Voltage to AVSS or DVSS (AVDD, DVDD ...
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AMD ISA ACCESS Parameter Symbol Parameter Description ti1 LA[23:17] valid setup to BALE ti2 BALE to BALE ti3 LA[23:17] valid hold from BALE LA[23:17] valid setup to CMD ti4 SA[16:0] valid setup to CMD ti7 CMD to CMD ti8 ti9 ...
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AC CHARACTERISTICS 5.0 V MEMORY BUS INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature Under Bias: Supply Voltage to AVSS or DVSS (AVDD, DVDD ...
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AMD MEMORY BUS WRITE ACCESS Parameter Symbol Parameter Description tmAD MA[16:0] valid from CLKIN CE active delay from CLKIN tmCD MWE active delay from CLKIN tmWD tmCQ MD[16:0] driven from CLKIN tmCV MD[16:0] valid from CLKIN Address Setup Time to ...
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AC CHARACTERISTICS 3.3 V MEMORY BUS INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature Under Bias: Supply Voltage to AVSS or DVSS (AVDD, DVDD ...
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AMD MEMORY BUS WRITE ACCESS Parameter Symbol Parameter Description tmAD MA[16:0] valid from CLKIN CE active delay from CLKIN tmCD MWE active delay from CLKIN tmWD tmCQ MD[7:0] driven from CLKIN tmCV MD[7:0] valid from CLKIN Address Setup Time to ...
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AC CHARACTERISTICS 5.0 V TAI INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature Under Bias: Supply Voltage to AVSS or DVSS (AVDD, DVDD ...
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AMD 5.0 V TAI INTERFACE AC CHARACTERISTICS Parameter Symbol Parameter Description TCLKIN CLKIN Period TCLIN CLKIN Low time TCHIN CLKIN High time TCLKIN CLKIN Period TCLIN CLKIN Low time TCHIN CLKIN High time TINHL CLKIN Fall time TINLH CLKIN Rise ...
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Notes: 1. Only applicable when TXC has been configured as an INPUT. 2. Only applicable when TXC has been configured as an OUTPUT. 3. MIN value not tested. 4. Parameter calculated from other parameters. 5. Clock period must correlate to ...
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AMD AC CHARACTERISTICS 3.3 V TAI INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature Under Bias: Supply Voltage to AVSS or DVSS (AVDD, DVDD ...
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V TAI INTERFACE AC CHARACTERISTICS Parameter Symbol Parameter Description tCLKIN CLKIN Period tCLIN CLKIN Low time tCHIN CLKIN High time tINHL CLKIN Fall time tINLH CLKIN Rise time tRXC RXC Period tCLRX RXC Low time tCHRX RXC High time ...
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AMD AC CHARACTERISTICS 5.0 AND 3.3 V USER PROGRAMMABLE PINS ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature Under Bias: Supply Voltage to AVSS or DVSS (AVDD, DVDD): . ...
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AC CHARACTERISTICS 5.0 AND 3.3 V IEEE 1149.1 INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature Under Bias: Supply Voltage to AVSS or DVSS (AVDD, DVDD ...
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AMD TIMING WAVEFORMS PCMCIA Bus Interface Waveforms REG (high) WAIT D o (Dout) Figure 4. PCMCIA MEMORY READ Access Timing Diagram REG WAIT D i (Din ...
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AVIGL REG t RGLIGL CE t ELIGL IORD t IGLIAL INPACK t IGLWTL WAIT D o (Dout) Figure 6. PCMCIA I/O READ Access Timing Diagram A ...
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AMD ISA Bus Interface Waveforms BALE AEN CMD IOCHRDY SD out (read (write) ** CMD = one of: MEMR , MEMW , IOR , IOW ...
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Memory Bus Interface Waveforms CLKIN CLKOUT (internal FCE, SCE, XCE MOE MWE (high (Din) Figure 9. Memory Bus READ Access Timing Diagram CLKIN CLKOUT (internal FCE, SCE, XCE ...
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AMD CLOCK WAVEFORMS CLKIN TXC RXC 152 CLIN 2 CHIN 0 INLH t INHL t CLKIN t CLTX 2 CHTX 0.8 V ...
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TAI WAVEFORMS CLKIN CLKOUT (internal) ICO* RCO** RCO** RCO** **ICO = Internally Controlled Output RXC RXD TXC (input) TXD TXC (output) TXD ...
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AMD PROGRAMMABLE INTERFACE WAVEFORMS CLKIN CLKOUT (internal) WAIT or IOCHRDY RCO** (data change) RCO** (drive change) RCO** (drive change) **RCO = Register Controlled Output Figure 14. Programmable Interface Timing Diagram 154 ...
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IEEE 1149.1 INTERFACE WAVEFORMS TCK TDI, TMS TDO Output Signals Input Signals Figure 15. IEEE ...
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AMD AC TEST REFERENCE WAVEFORMS 5.0 V PCMCIA AC Test Reference Waveform This waveform indicates the AC testing method em- ployed for all signals that are PCMCIA bus signals when 2.8 input 0.5 2.8 output 0.5 Figure 16. 5.0 V ...
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V NON-PCMCIA AC TEST REFERENCE WAVEFORM This waveform indicates the AC testing method em- ployed for all signals that are not PCMCIA bus signals when the appropriate power supply pins are set to 5.0 V (i.e., VDDT, VDDU1, VDDU2, ...
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AMD PHYSICAL DIMENSIONS PQT144 144-Pin Thin Quad Flat Pack (measured in millimeters) 144 1 1.35 1.45 1.00 REF. *For reference only. BSC is an ANSI standard for Basic Space Centering. Trademarks Copyright 1997 Advanced Micro Devices, Inc. All rights reserved. ...
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APPENDIX A Typical Am79C930 System Application Host Computer Figure 1: Typical Am79C930 System Application The typical Am79C930 application Am79C930 device, a Flash memory device (up to 128 Kbytes), an SRAM memory device (up to 128 Kbytes), a network transceiver unit, ...
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AMD 1. Command and status communication 2. Data buffer areas 3. Am79C930 80188 core variable space After performing these functions, the device driver will enable the 80188 core by writing to a register to release the RESET of the Am79C930 ...
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Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, b IMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, ...