AM79C930VC/W AMD [Advanced Micro Devices], AM79C930VC/W Datasheet - Page 71
![no-image](/images/no-image-200.jpg)
AM79C930VC/W
Manufacturer Part Number
AM79C930VC/W
Description
PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C930VCW.pdf
(161 pages)
- Current page: 71 of 161
- Download datasheet (678Kb)
The second mapping scheme (scheme “B”) places 32K
of the SRAM, the 32 TIR registers, the 16 MIR registers,
and the 16 XCE locations into the lowest 32K of memory
space, and then maps the upper 96K of Flash memory
to memory locations 32K through 128K. All 128K of the
Flash memory is also available at the uppermost 128K
memory locations of the 80188 core’s address space.
This scheme allows the LMCS register of the 80188
core be set to 07F8h or 0FF8h or 1FF8h. The UMCS
register of the 80188 core must be set to E038h. Also
2 0000h–D FFFFh
E 0000h–F FFFFh
2 0000h–D FFFFh
E 0000h–F FFFFh
0 0480h–1 FFFFh
0 8000h–1 FFFFh
0 0000h–0 03FFh
0 0000h–0 03FFh
0 0480h–0 7FFFh
0 0400h–0 041Fh
0 0420h–0 042Fh
0 0430h–0 043Fh
0 0440h–0 047Fh
0 0400h–0 041Fh
0 0420h–0 042Fh
0 0430h–0 043Fh
0 0440h–0 047Fh
80188 Address
80188 Address
in Memory
in Memory
80188 Core Memory Map Using Scheme “A”, LMCS=1FF8h, UMCS=E038h, MIR0[6]=0
80188 Core Memory Map Using Scheme “B”, LMCS=1FF8h, UMCS=E038h, MIR0[6]=1
Active 80188
Active 80188
Chip Select
Chip Select
don’t care
none
none
UCS
UCS
LCS
LCS
LCS
LCS
LCS
LCS
LCS
LCS
LCS
LCS
LCS
LCS
P R E L I M I N A R Y
Chip Select
Chip Select
Am79C930
Am79C930
Active
Active
none
none
none
none
none
none
none
none
SCE
XCE
SCE
FCE
SCE
XCE
SCE
FCE
FCE
Am79C930
required is that bit 6 of the MIR0 register (the mapping
select bit) is set to 1. Note that with mapping scheme
“B”, a maximum of 32K–128 bytes of SRAM space is
available for use. The advantage of mapping scheme
“B” is that when all 80188 firmware can fit into 32K of
Flash memory space and the SRAM memory require-
ment for the application is less than or equal to 32K, then
all 80188 operations occur within a single 64K
memory segment.
1K–128 bytes
1K–128 bytes
768 Kbytes
128 Kbytes
768 Kbytes
96 Kbytes
96 Kbytes
1 Kbytes
1 Kbytes
32 bytes
16 bytes
16 bytes
64 bytes
32 bytes
16 bytes
16 bytes
64 bytes
Size of
Size of
Space
Space
128K–
32K–
these areas is currently undefined
these areas is currently undefined
Reserved for future use–access to
Reserved for future use–access to
SRAM Memory 0 0480h–1 FFFFh
SRAM Memory 0 0480h–1 FFFFh
SRAM Memory 0 0000h–0 03FFh
Flash Memory 0 0000h–1 FFFFh
SRAM Memory 0 0000h–0 03FFh
Flash Memory 0 8000h–1 FFFFh
Flash Memory 0 0000h–1 FFFFh
Physical Location of Memory
Physical Location of Memory
XCE locations 0–15
XCE locations 0–15
Undefined
Undefined
MIR 0–15
MIR 0–15
TIR 0–31
TIR 0–31
AMD
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