M36P0R9060N0ZANE NUMONYX [Numonyx B.V], M36P0R9060N0ZANE Datasheet - Page 11
M36P0R9060N0ZANE
Manufacturer Part Number
M36P0R9060N0ZANE
Description
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 64 Mbit (Burst) PSRAM, 1.8V supply, Mux I/O, Multi-Chip Package
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet
1.M36P0R9060N0ZANE.pdf
(23 pages)
M36P0R9060N0
2.11
2.12
2.13
2.14
2.15
2.16
PSRAM Chip Enable input (E
The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted
(V
Power-down mode, according to the RCR (Refresh Configuration Register) setting.
PSRAM Write Enable (W
Write Enable, W
device is in Write mode and Write operations can be performed either to the configuration
registers or to the memory array.
PSRAM Output Enable (G
When held Low, V
PSRAM.
PSRAM Upper Byte Enable (UB
The Upper Byte En-able, UB
DQ15) to or from the upper part of the selected address during a Write or Read operation.
PSRAM Lower Byte Enable (LB
The Lower Byte Enable, LB
DQ7) to or from the lower part of the selected address during a Write or Read operation.
If both LB
or transmitting data. Although the device will seem to be deselected, it remains in an active
mode as long as E
PSRAM Configuration Register Enable (CR
When this signal is driven High, V
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR)
according to the value of A19.
IH
), the device is disabled, and goes automatically in low-power Standby mode or Deep
P
and UB
P
, controls the Bus Write operation of the PSRAM. When asserted (V
IL
P
P
, the Output Enable, G
remains Low.
are disabled (High), the device will disable the data bus from receiving
P
, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
P
, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
IH
, bus read or write operations access either the value of
P
)
P
)
P
, enables the Bus Read operations of the
P
)
P
P
)
)
P
)
2 Signal descriptions
IL
), the
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