AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 171
AM8530H
Manufacturer Part Number
AM8530H
Description
Serial Communications Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM8530H.pdf
(194 pages)
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AMD
The data bus between the 68000 and the Am8530H are directly linked together. The
Am29806 decodes the address and generates CS for the peripheral and produces ANYE,
which is used by the 74LS164, to generate Wait States. The 74LS164 controls the num-
ber of wait states by the “C” input which in turn controls the DTACK signal to the CPU.
This allows RD and WR to obtain the required 400 ns width. A
to the Am8530H while the remaining address lines are connected to the Am29809 ad-
dress comparator.
The Am29809 Comparator and the Am29806 Comparator/Decoder provides high-speed
address selection as well as an open collector acknowledge driver. This allows memories
and peripherals to be conveniently wire-ORed to the processor’s DTACK pin. This inter-
face does not provide a hardware reset; therefore, it is necessary to do a dummy read to
the control port before issuing a software reset.
7–22
Figure 7–12. Am8530H to 68000 Connection with Interrupts Using SSI and MSI
68000
DTACK
IPL 0
IPL 1
IPL 2
FC 0
FC 1
FC 2
CLK
A 3
R/W
A 23
A 18
A 11
A 4
A 10
A 5
LDS
•
•
•
AS
A 1
CLK
OSC
74LS04
A 0
A 1
A 2
A
B
C
74LS148
74LS138
V CC
8
6
EI
CLK/2
74LS04
7
0
1
2
3
4
S 1
S 0
A 5
A 0
A 7
A 0
ACK
Am29809
•
•
•
Am29806
•
•
•
74LS32
74LS32
E OUT
ANYE
G
G
INTA
BRIDGES FOR SETTING
E OUT
BIP SWITCHES OR
OTHER
INTRRUPTS
A 1
A 2
A 3
CLK
ADDRESS
SOLDER
A
B
C
G2A
CP
D
74LS138
74LS74
PRE
Q
1
2
3
4
CLK
NUMBER OF WAIT STATES
74LS04
CONNECT FOR DESIRED
74LS04
INTA
FOR OTHER
INTERRUPTING
DEVICES
74LS02
CLK
74LS16
CLR
74LS164
A
B
CLR
Q B
OC
1
74LS04
1
A
74LS164
Q C
generates the C/D input
2
SCC Application Notes
B
74LS04
Q D
CLK
3
CLK/2
CLK
Q E
Q F
74LS02
PCLK
WR
CS
D/C
RD
INT
INTA
Am8530H