AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 24

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
System Interface
2.4
REGISTER ACCESS
The registers in the SCC are accessed in a two-step process, using a Register Pointer to
perform the addressing. To access a particular register, the pointer bits must be set by
writing to WR0. The pointer bits may be written in either channel because only one set
exists in the SCC. After the pointer bits are set, the next read or write cycle of the SCC
having D/C Low will access the desired register. At the conclusion of this read or write
cycle, the pointer bits are automatically reset to ‘0’, so that the next control write will be to
the pointers in WR0.
A read from RR8 (the Receive Buffer) or a write to WR8 (Transmit Buffer) may either be
done in this fashion or by accessing the SCC having the D/C pin High. A read or write
with D/C High accesses the receive or transmit buffers directly, and independently, of the
state of the pointer bits. This allows single-cycle access to the receive or transmit buffers
and does not disturb the pointer bits. The fact that the pointer bits are reset to ‘0’, unless
explicitly set otherwise, means that WR0 and RR0 may also be accessed in a single cy-
cle. That is, it is not necessary to write the pointer bits with ‘0’ before accessing WR0 or
RR0. There are three pointer bits in WR0, and these allow access to the registers with
addresses 0 through 7. Note that a command may be written to WR0 at the same time
that the pointer bits are written. To access the registers with addresses 8 through 15, a
special command (point high in WR0) must accompany the pointer bits. This precludes
concurrently issuing a command (point high in WR0) when pointing to these registers.
The SCC register map is shown in Table 2–2. PNT
, PNT
and PNT
are bits D2, D1 and
2
1
0
D0 in WR0, respectively.
If for some reason the state of the pointer bits is unknown, they may be reset to ‘0’ by per-
forming a read cycle with the D/C pin held Low. Once the pointer bits have been set, the
desired channel is selected by the state of the A/B pin during the actual read or write of
the desired register.
A/B, D/C
Address Valid
INTACK
CE
RD
D 0 - D
Data Valid
7
10216A-009A
Figure 2–1. SCC Read Cycle
2–6