AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 5
AM8530H
Manufacturer Part Number
AM8530H
Description
Serial Communications Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM8530H.pdf
(194 pages)
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Table of Contents
Chapter 4
3.9
Data Communication Modes Functional Description
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Block Transfers
3.9.1 Wait on Transmit
3.9.2 Wait on Receive
3.9.3 DMA Requests
Introduction
Protocols
4.2.1 Asynchronous
4.2.2 Synchronous Transmission
Mode Selection
Receiver Overview
4.4.1 Rx Character Length
4.4.2 Rx Parity
4.4.3 Rx Modem Control
Transmitter Overview
4.5.1 Tx Character Length
4.5.2 Tx Parity
4.5.3 Break Generation
4.5.4 Transmit Modem Control
4.5.5 Auto RTS Reset
Asynchronous Mode Operation
4.6.1 Receiver Operation
4.6.2 Transmitter Operation
SDLC Mode Operation
4.7.1 Receiver Operation
4.7.2 SDLC Mode CRC Polynomial Selection
3.9.3.1 DMA Request on Transmit
3.9.3.2 DMA Request on Transmit
3.9.3.3 DTR/REQ Deactivation Timing
3.9.3.4 DMA Request on Receive (using W/REQ)
4.2.2.1 Synchronous Character-Oriented
4.2.2.2 Synchronous Bit-Oriented
4.6.1.1 Receiver Initialization
4.6.1.2 Framing Error
4.6.1.3 Break Detection
4.6.1.4 Clock Selection
4.6.2.1 Transmitter Initialization
4.6.2.2 Stop Bit Selection
4.7.1.1 Flag Detect Output
4.7.1.2 Receiver Initialization
4.7.1.3 10x19-Bit Frame Status FIFO
4.7.1.4 Address Search Mode
4.7.1.5 Abort Detection
4.7.1.6 Residue Bits
4.7.2.1 Rx CRC Initialization
4.7.2.2 Rx CRC Enabling
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(using W/REQ)
(using DTR/REQ)
Protocol
4.7.1.3.1 FIFO Enabling/Disabling
4.7.1.3.2 FIFO Read Operation
4.7.1.3.3 FIFO Write Operation
4.7.1.3.4 14-Bit Byte Counter
4.7.1.3.5 Am85C30 Frame Status
4.7.1.3.6 Am85C30 Aborted Frame
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FIFO Operation Clarification
Handling When Using the 10x19
Frame Status FIFO
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AMD
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3–15
3–16
3–16
3–17
3–17
3–18
3–19
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4–3
4–3
4–3
4–4
4–4
4–4
4–5
4–6
4–7
4–8
4–9
4–9
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4–11
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4–12
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