AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 70

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
4.7.1.3.5
In an effort to make the 10x19 Frame Status FIFO (FSF) useful for high-speed reception
of packets, the lock on the 3-byte receive FIFO that occurs after special conditions in two
of the receive interrupt modes was removed. The benefit of this operation is that the user
can receive multiple frames of SDLC data before having to service the interrupt. Competi-
tion 85C30 freezes the Rx FIFO after every frame, so the user could lose frames of data
between the end of the first frames and Reset Error command. In this case the user must
service interrupts for every frame of data on the competition 85C30, defeating the pur-
pose of the FIFO. AMD allows the user to receive up to 10 frames of data before having
to service the interrupt, thus obtaining the maximum (desired) utilization of the FSF.
A clarification of the enhanced operation is given below. the removal of the lock on the
Receive Data 3-byte FIFO affects the device when it is programmed in the “Interrupt on
First Receive Character of Special Condition” or “Interrupt on Special Condition Only”
modes.
1. When the 10x19 Frame Status FIFO (FSF) is not enabled, the 3-byte Receive FIFO
2. When the FSF is enabled:
4–18
(Rx FIFO) locks when a special condition is received until the Reset Error command is
issued. DMA is disabled when the Rx FIFO locks until the Reset Error command is
issued (same as old operation).
a. The 3-byte Receive FIFO never locks.
b. DMA is disabled only on overrun (i.e. overruns do not lock the Rx FIFO, but do
c. Interrupts are generated and remain active until the RESET ERROR command
d. Interrupt vectors (in Read Register 2B) are modified as follows. There are two
0
F
Don't Load
Counter On
1st Flag
Reset Byte
Counter Here
disable DMA).
To reenable DMA after an overrun, the following sequence must be used:
i. Read and discard ALL entries in the Receive Data 3-byte FIFO.
ii. Issue the Error Reset command.
iii. Note that if an additional byte of data is received between the time that the
is issued.
bit patterns for Receiver Interrupts, x11-Special Receive condition, and x10
Receive Character Available. Refer to Figure 3–2 (page 3–6) and Table 6–4
(page 6–19) of this manual.
1
A
Receive Data FIFO is emptied and the ERROR RESET command is issued.
DMA will NOT unlock. This signals the user that corrupt data remains in the
Receive Data FIFO. The user must read and discard all entries in the Receive
Data 3-byte before DMA will reenable. Note that an additional ERROR RESET
is not required.
2
D
Am85C30 Frame Status FIFO Operation Clarification
Internal Byte Strobe
Increments Counter
3
D
Figure 4–14. Frame Status FIFO Control Timing
4
D
5
D
6
C
Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR
7
C
Data Communication Modes Functional Description
F
0
F
Reset
Byte Counter
1
A
2
D
Internal Byte Strobe
Increments Counter
D
3
D
4
D
5
6
C
Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR
C
7
10216A-012A
0
F