HI-3110 HOLTIC [Holt Integrated Circuits], HI-3110 Datasheet - Page 15

• Manufacturer Part Number: HI-3110
• Description: Avionics CAN Controller with Integrated Transceiver
• Manufacturer: HOLTIC [Holt Integrated Circuits]

Phase Buffer Segment 1 and Phase Buffer
Segment 2 (Phase Seg1 and Phase Seg2)
The phase buffer segments are used to compensate for
phase errors on the bus. Phase Seg1 can be lengthened or
Phase Seg2 can be shortened duringthe re-synchronization
bit period automatically by the HI-3110 so that the bit time
can be adjusted to account for phase errors. The upper limit
by which the lengthening ( or shortening) can occur is set by
the
more detail below.
Sample Point
The sample point is the point in the bit time at which the bit
logic level is interpreted. It is located at the end of Phase
Seg1. The HI-3110 also allows three sample points to be
taken. In this case, two other sample points are taken prior
to the end of Phase Seg1 (at one-half TQ intervals) and the
value of the bit is determined by a majority decision. Three
sample points are typically only used at low bit rates.
ARINC 825 states that there shall be only one sample per bit,
taken at the end of Phase Seg1.
The time required for the logic to determine the bit level of a
sampled bit is known as the
(IPT)
Since Phase Seg2 occurs after the sample point, Phase
Seg2 must be greater than or equal to the worst case IPT
(2Tq).
Phase Errors (e)
If a bit edge occurs within the Sync Seg as expected, there is
no phase error (e = 0). However, if an edge occurs outside
Sync Seg, a phase error is deemed to have occurred. If the
edge occurs after Sync Seg (edge occurs “late”), the phase
error is positive (e > 0), whereas if the edge occurs before
Sync Seg (edge occurs “early”), the phase error is negative
(e < 0).
Synchronization
Synchronization is carried out only on recessive-to-
dominant bit edges and is used to ensure the bit times of all
nodes on the bus are synchronized. This is necessary for
arbitration and message acknowledgment to function
properly. Only one synchronization can occur per bit time.
Hard synchronization
Sync Seg, regardless of the phase error.
synchronization only occurs on reception of the start of a
re-synchronization jump width (SJW),
. According to the standard, IPT can be up to 2Tq.
forces the bit edge to lie within the
information processing time
HOLT INTEGRATED CIRCUITS
explained in
Note:
Hard
HI-3110
15
frame.
Re-synchronization
lengthening of the bit time such that the position of the
sample point is shifted with respect to the edge causing the
re-synchronization.
the magnitude of the phase error, up to a maximum of SJW.
For e < 0
phase error, up to a maximum of SJW.
Examples
1) CAN bit rate (BR) = 125kHz, f
Assume sample point (at end of TSeg1) will occur at 75% of
bit time. Hence, for Sync Seg = 1Tq, TSeg1 = 5 Tq and
TSeg2 = 2Tq. Therefore, total bit time will be 8Tq. Chose
SJW = 1Tq.
For 125kHz, the bit time needs to be 1/125kHz = 8μs.
Hence, 1Tq = 1μs. Using equation (1) => BRP = 6.
2) CAN bit rate (BR) = 1MHz, f
Assume sample point (at end of TSeg1) will occur at 75% of
bit time. For Sync Seg = 1Tq, then TSeg1 = 11Tq and TSeg2
= 4Tq. Therefore, total bit time will be 16Tq. Chose SJW =
1Tq.
For 1MHz, the bit time needs to be 1/1MHz = 1μs. Hence,
1Tq = 62.5ns. Using equation (1) => BRP = 1.
Note:
requirement of ARINC 825. The oscillator frequency must
be chosen such that a valid value of BRP (integer) can
generate the TQ clock (e.g. in example 2 above, using a
lower oscillator frequency than 32MHz results in BRP < 1).
Choosing the sample point at 75% of the bit time is a
, Phase Seg 2 is shortened by the magnitude of the
For e > 0
results in the shortening or
, Phase Seg 1 is lengthened by
OSC
OSC
= 32MHz.
= 12MHz.