HI-3110 HOLTIC [Holt Integrated Circuits], HI-3110 Datasheet - Page 21

• Manufacturer Part Number: HI-3110
• Description: Avionics CAN Controller with Integrated Transceiver
• Manufacturer: HOLTIC [Holt Integrated Circuits]

The TEC register reflects the current value of the CAN Transmit Error Counter. This register can be written by SPI command for test
purposes.
Bit Name
7-0 TEC7:0
The REC register reflects the current value of the CAN Receive Error Counter. This register can be written by SPI command for test
purposes.
Bit Name
7-0 TEC7:0
TRANSMIT ERROR COUNTER REGISTER: TEC
(Write, SPI Op-code 0x26)
(Read, SPI Op-code 0xEC)
RECEIVE ERROR COUNTER REGISTER: REC
(Write, SPI Op-code 0x24)
(Read, SPI Op-code 0xEA)
R/W
R/W
R/W
R/W
Default Description
Default Description
0x00
0x00
Transmit Error Counter bits <7:0>.
0
96 TEC
may be used to generate a hardware interrupt if ERRWIE bit is set in STATFE register.
128
register. ERRP also set in STATF register. This may be used to generate a hardware interrupt if
ERRPIE bit is set in STATFE register.
TEC > 255: Bus-off status. Bus-off flags, BUSOFF, set in ERR and STATF registers. The
latter may be used to generate a hardware interrupt if BUSOFFIE bit is set in STATFE register.
The HI-3110 will, after entering bus-off state, automatically recover to error active status
without host intervention if the BOR bit is set in control register CTRL0 and 128 x 11
consecutive recessive bits are detected on the bus. If the BOR bit is not set, bus-off recovery is
managed by the host.
Receiver Error Counter bits <7:0>.
0
96
may be used to generate a hardware interrupt if ERRWIE bit is set in STATFE register.
128
register. ERRP also set in STATF register. This may be used to generate a hardware interrupt if
ERRPIE bit is set in STATFE register.
£
£
£
£
TEC
REC
£
£
REC
TEC 255: Error passive status. Transmit error passive flag, TXERRP, set in ERR
REC
£
£
£
HOLT INTEGRATED CIRCUITS
£
£
95: Error active status.
95: Error active status.
£
127: Error active status. Error warning flag, ERRW, set in STATF register. This
127: Error active status. Error warning flag, ERRW, set in STATF register. This
255: Error passive status. Receive error passive flag, RXERRP, set in ERR
HI-3110
MSB
MSB
7
7
21
6
6
5
5
REC7:0
TEC7:0
4
4
3
3
2
2
1
1
LSB
LSB
0
0