HYS64D128320GU-6-B INFINEON [Infineon Technologies AG], HYS64D128320GU-6-B Datasheet - Page 20

• Manufacturer Part Number: HYS64D128320GU-6-B
• Description: 184-Pin Unbuffered Dual-In-Line Memory Modules
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 13
Parameter
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
1) 0 °C ≤
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
11) For each of the terms, if not already an integer, round to the next highest integer.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
(DDR400)
level for signals other than CK/CK, is
t
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
system performance (bus turnaround) degrades accordingly.
ns, measured between
cycle time.
HZ
and
T
t
A
LZ
AC Timing - Absolute Specifications for PC3200 and PC2700
≤ 70 °C
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
; V
DDQ
V
IH(ac)
= 2.5 V ± 0.2 V,
and
V
IL(ac)
V
REF
V
REF
Symbol
t
t
t
t
t
t
t
.
RRD
WR
DAL
WTR
XSNR
XSRD
REFI
V
. CK/CK slew rate are ≥ 1.0 V/ns.
DD
stabilizes.
= +2.5 V ± 0.2 V (DDR333);
–5
DDR400B
Min.
10
15
2
75
200
—
20
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Max.
—
—
—
—
—
7.8
Unbuffered DDR SDRAM Modules
–6
DDR333
Min.
12
15
1
75
200
—
V
DDQ
t
= 2.6 V ± 0.1 V,
CK
Max.
—
—
—
—
—
7.8
is equal to the actual system clock
t
DQSS
Electrical Characteristics
10042003-RYU3-RQON
Unit
ns
ns
t
t
ns
t
µs
.
CK
CK
CK
V
DD
Rev. 1.0, 2004-05
= +2.6 V ± 0.1 V
Note/ Test
Condition
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
V
1)
TT
.