SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 128

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.4.5
7.4.6
128
Register Name: COR5
Register Description: Channel Option Register 5
Access: Read/Write
Register Name: LIVR
Register Description: Local Interrupt Vector
Access: Read/Write
ISTRIP
Bit 7
Bit 7
X
Bit
4:3
1:0
7
6
5
2
Channel Option Register 5
Local Interrupt Vector Register
The LIVR is used only during hardware-activated service-acknowledge cycles. Host software
loads desired information into the most-significant five bits; the least-significant three bits are not
used. When the CD1284 is setting up a service request, it overlays the five most-significant bits of
the LIVR into appropriate interrupt vector register (RIVR, TIVR, PIVR, and MIVR) and sets the
least-significant three bits as required for the service request vector type. (See RIVR, TIVR, PIVR,
and MIVR descriptions). Refer to
register.
ISTRIP: This bit enables stripping of the most-significant bit (bit 7) on all received characters. ‘1’ enables the
function.
LNext Enable: When this bit is set, characters following an LNext character (as programmed by the LNC
register) are not processed as a special character.
Character Matching on Error: If this bit is set, character matching occurs on both good and error characters.
If the bit is cleared, matching occurs on good characters only.
These bits must always be ‘0’.
End of Break Detect: If this bit is set, the CD1284 after detecting and reporting a line-break condition,
searches for the end of a break and reports it by an exception service request with the End of Break status in
the RDSR (see RDSR description
Carriage Return (CR) and New Line (NL) Processing – Transmit: These two bits define any actions taken on
characters in the transmit data stream.
Bit 6
Bit 6
LNE
X
ONLCR
0
0
1
1
CMOE
Bit 5
Bit 5
X
OCRNL
0
1
0
1
Section 7.2.4 on page
Bit 4
Bit 4
X
0
Section 7.7.5 on page 138
No action.
Transmit CR changed to NL.
Transmit NL changed to CRNL.
Transmit CR changed to NL; NL changed to CRNL.
Description
Bit 3
Bit 3
X
0
115).
Action
Bit 2
Bit 2
EBD
for a more detailed description of this
IT2
ONLCR
Bit 1
Bit 1
IT1
8-Bit Hex Address: 18
8-Bit Hex Address: 1F
Default Value: 00
Default Value: 00
Datasheet
OCRNL
Bit 0
Bit 0
IT0