SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 163

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

8.3.2
Datasheet
DMAACK*
DMAREQ*
DMAREQ*
DMAACK*
DB[15:0]
DB[15:0]
NOTE:
NOTE: The data is sampled on the third rising edge of CLK following the assertion of DMAACK*. If DMAACK* is held
Figure 27. Asynchronous DMA Write Cycle Timing
Figure 28. Asynchronous DMA Write Cycle Timing (Two Back-to-Back DMA Writes)
CLK
CLK
active for more than three CLK cycles then the next DMA write cycle will simply be delayed, but the data will still be
sampled on the third rising CLK edge following the assertion of DMAACK*. If DMAACK* is active for
n the data is still sampled on the third rising CLK edge following the assertion of DMAACK* (provided that
DMAACK* is active long enough for the device to lastch it. Due to this somewhat synchronous behavior, care must
be taken to guarantee that the data is valid at this CLK edge. Do not assume that the data will be sampled on the
deassertion of DMAACK*.
Figure 27
Synchronous Timing
Use the following table as a reference to timing parameters of figures in this section.
is still valid, however,
DMAACK* SYNCHRONIZED
Figure 28
HERE
t
IEEE 1284-Compatible Parallel Interface Controller — CD1284
30
t
31
t
19
t
24
DMAACK* LATCHED
illustrates more robust timing.
HERE
t
32
SEE NOTE
DATA SAMPLED
VALID
HERE
DMAACK* SYNCHRONIZED
t
28
HERE
MAY CHANGE
t
29
t
t
30
31
t
21
VALID
DATA SAMPLED
VALID
t
32
HERE
3 CLKs, the
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