SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 141

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

7.7.9
Datasheet
Register Name: PFEP
Register Description: Parallel FIFO Empty Pointer
Access: Read/Write
Bit 7
0
Bit
7
6
5
4
3
2
1
0
Parallel FIFO Empty Pointer Register
This register holds the internal empty location pointer of the FIFO. It identifies the location in the
FIFO from which the next byte of data transfers from the FIFO.
FIFO Reset: This bit must be set together with the correct value of DMAdir to properly initialize the data
pipeline and FIFO registers for data transfer or when a new data transfer direction is desired. Any data
remaining in the FIFO is discarded. The FIFO remains in reset mode until this bit is cleared with a second
register write operation.
DMA Enable: This bit must be set for DMA requests to move data to or from the FIFO to be made. When
DMAen
Receive mode, if the threshold is equalled or exceeded, DMAREQ* is asserted and causes DMA data
transfers of whole (2-byte) words from the FIFO by the data pipeline. In Transmit mode, if the amount of data
in the FIFO is equal to or less than the threshold, DMAREQ* is asserted causing DMA data transfers of whole
(2-byte) words to the FIFO by the data pipeline.
DMA Direction: This bit sets the direction of transfer between the parallel FIFO and system memory. If
DMAdir
The desired DMAdir value must be set together with FIFOres when initializing the FIFO logic for data transfer.
Once a DMAdir value is set and the FIFOres is complete, that DMAdir selection must be maintained during
any other changes to the control bits of the PFCR.
Note: This bit sets the direction of the channel, even when DMA is not enabled. The proper direction must be
Interrupt Enable: This is the master interrupt enable for the parallel channel. This bit must be set for any
interrupts generated by the data pipeline, parallel port, or error status. In Poll-mode operation, host software
toggles this bit to signal the completion of the service-acknowledge cycle. Toggling this bit updates the state
of SVCREQP* and the PIR according to the current state of PCISR, DERR, and PFSR. For this reason,
PCISR, DERR, and PFSR should be read and cleared at the end of the service routine to ensure that no
requests were skipped. This is because an edge-sensitive interrupt controller may not detect a request active
when the program returns from the service routine.
RLE Enable: The state of this bit enables RLE encoding/decoding for the direction defined by DMAdir. The
RLEen bit effects the flow of data through the data pipeline in the transmit direction. Data flow into the FIFO is
managed in such a way that PFHR1 and PFHR2 are kept full to permit evaluation of data sequences for
possible compression. The effect is that following any data transfer while RLEen is set, the final 2 bytes
written to the DMABUF register are kept in PFHR1 and PFHR2. To allow these bytes to be moved into the
FIFO or to make room in PFHR1 for a tagged data transfer, RLEen must be ‘0’ and both DMAen and
DMAbufWe must be ‘0’.
Set TAG: This bit specifies that the next character written to the parallel channel by the PFHR1 register is to
be tagged as an ECP or EPP special character (for a detailed explanation of the special handling of these
characters, see
time a tagged character is to be written.
Error Interrupt Enable: This bit enables a non-zero DataErr status to cause an interrupt if IntEn is also set.
DMA Buffer Write Enable: This bit must be set to enable host writes to the DMABUF register. It also enables
the FIFO data pipeline to empty the DMABUF register when written to by the host system. In this case, the
system writes to the DMA buffer (without DMA transfers) providing a low-performance alternative to DMA
transfers.
Bit 6
0
set regardless of the DMAen bit.
1, The PFQR quantity value is compared with the PFTR user-programmed threshold value. In
1, the direction is transmit (system memory to the parallel FIFO); if it is ‘0’, the direction is receive.
Section
Bit 5
5.13). The setTAG bit is cleared by a write to PFHR1 thus, this bit must be set each
IEEE 1284-Compatible Parallel Interface Controller — CD1284
Bit 4
6-bit binary FIFO Pointer Value
Description
Bit 3
Bit 2
Bit 1
8-Bit Hex Address: 39
Default Value: 00
Bit 0
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