SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 21

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

Datasheet
DS*
BYTESWAP
DTACK*
DMAREQ*
DMAACK*
SVCREQR*
SVCACKR*
SVCREQT*
SVCACKT*
SVCREQP*
SVCACKP*
SVCREQM*
SVCACKM*
DGRANT*
Symbol
Table 1. Pin Descriptions (Sheet 2 of 4)
Pin No.
77
82
75
13
12
61
62
63
64
68
69
66
67
70
Type
OD
OD
OD
OD
AR
O
I
I
I
I
I
I
I
I
ACTIVE-LOW DATA STROBE: During an active I/O cycle, the input DS* strobes data
into On-Chip registers on write cycles or enables data onto the data bus during read
cycles. DS* is ignored during DMA operations.
BYTESWAP: This input determines the byte order for 2-byte DMA transfers and for
writes to the DMA Buffer register. When BYTESWAP is ‘1’, then Data Bus bits [15:8]
are driven with the byte transferred first on the parallel port bus. Data Bus bits [7:0] are
driven with the byte transferred second on the parallel port bus. When BYTESWAP is
‘0’, the data order is reversed, bits [7:0] are driven with the byte transferred first and
bits [15:8] are driven with the byte transferred second.
ACTIVE-LOW DATA TRANSFER ACKNOWLEDGE: This output indicates: 1) when
the device completes the requested I/O operation, and, 2) when the current cycle can
finish. This signal can implement wait-state insertion for the local CPU. DTACK* does
not activate on DMA cycles.It is an active-release output, driving to a logic ‘1’ then
releasing to OD. DTACK* must be ties to external V
ACTIVE-LOW DMA REQUEST: When the internal control bit DMAen is set, the output
DMAREQ* is asserted if internal FIFO conditions warrant a DMA transfer. DMAREQ*
is deasserted on the falling edge of DMAACK* when DMA transfers cannot continue
past the current transfer.
ACTIVE-LOW DMA ACKNOWLEDGE: This input is never asserted unless in
response to a DMAREQ* from the chip. DMAACK* is the only bus handshake signal
recognized during a DMA transfer. (CS* must be high whenever DMAACK* is
asserted). The direction of DMA transfer is determined by internal control bit DMAdir.
ACTIVE-LOW SERVICE REQUEST RECEIVE: This is an open-drain output and must
be tied to external V
receive FIFO has either reached the programmed threshold or an exception condition
exists that requires CPU attention.
ACTIVE-LOW SERVICE ACKNOWLEDGE RECEIVE: This input is driven low during
service acknowledge cycles to begin servicing a receive-service request. It must not
be driven active except in response to a receive-service request presented by the
device.
ACTIVE-LOW SERVICE REQUEST TRANSMIT: This is an open-drain output and
must be tied to external V
transmit FIFO or serial transmitter is empty and requires CPU attention.
ACTIVE-LOW SERVICE ACKNOWLEDGE TRANSMIT INPUT: This input is driven
low during service acknowledge cycles to begin servicing a transmit-service request. It
must not be driven active except in response to a transmit-service request presented
by the device.
ACTIVE-LOW SERVICE REQUEST PARALLEL: This is an open-drain output and
must be tied to external V
FIFO threshold or FIFO full/empty conditions.
ACTIVE-LOW SERVICE ACKNOWLEDGE PARALLEL: This input cannot be driven
active except in response to a parallel service request presented by the device.
ACTIVE-LOW SERVICE REQUEST STATUS (Modem): This is an open-drain output
that must be tied to external V
programmed modem signal change occurs and requires CPU attention.
ACTIVE-LOW SERVICE ACKNOWLEDGE STATUS (Modem): This input is driven
low during service acknowledge cycles to begin servicing a modem-service request. It
must not be driven active except in response to a modem-service request presented
by the device.
ACTIVE-LOW DAISY GRANT: This input is driven active during service acknowledge
cycles to enable the daisy-chain function. This input, when qualified with DS* and a
valid service acknowledge (SVCACKR*, SVCACKT*, SVCACKM*, or SVCACKP*),
activates the CD1284 service-acknowledge cycle.
IEEE 1284-Compatible Parallel Interface Controller — CD1284
CC
through a pull-up resistor. When active, the device serial-
CC
CC
through a pull-up resistor. SVCREQP* is not activated by
through a pull-up resistor. When active, the device serial
CC
through a pull-up resistor. When active, a
Description
cc
through a pull-up resistor.
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