SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 168

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
168
DMAREQ*
DMAACK*
DMAREQ*
DMAACK*
DB[15:0]
DB[15:0]
NOTE: The data is driven (t
Figure 32. Synchronous DMA Write Cycle Timing
Figure 33. Synchronous DMA Read Cycle Timing
NOTE: The data is sampled on the second rising edge of CLK following the assertion of DMAACK*, as long as
CLK
CLK
time (t
cycle is simply delayed, but the data is still driven (t
of DMAACK*.
setup time (t
cycle is simply delayed; the data is still sampled on the second rising CLK edge following the assertion
of DMAACK*.
(Two Back-to-Back 3-Cycle DMA Writes)
(Two Back-to-Back 3-Cycle DMA Reads)
18
) is met. If DMAACK* is held active for more than 2.5 CLK cycles after C1 falling edge, then the next DMA
C
C
18
) is met. If DMAACK* is held active for more than 2.5 CLK cycles, then the next DMA
t
15
t
15
24
t
) after the first falling edge of CLK following the assertion of DMAACK*, as long as setup
18
SEE NOTE
C1
t
18
C1
DATA SAMPLED
C2
C2
t
17
HERE
SEE NOTE
VALID
24
VALID
t
C3
) after the first falling CLK edge following the next assertion
22
C3
t
25
t
25
t
16
C1
C1
t
SEE NOTE
24
t
18
t
16
C2
C2
t
SEE NOTE
17
VALID
VALID
C3
DATA SAMPLED
C3
t
22
HERE
t
23
Datasheet
C
C