ELANSC310 AMD [Advanced Micro Devices], ELANSC310 Datasheet - Page 36

• Manufacturer Part Number: ELANSC310
• Description: Single-Chip, 32-Bit, PC/AT Microcontroller
• Manufacturer: AMD [Advanced Micro Devices]

LRDY
Local Bus Device Ready (Input; Active Low)
This signal is used by the local bus devices to terminate
the current bus cycle.
M/IO
Local Bus Memory/I/O (Output; Active Low)
This signal indicates to the local bus devices that the
current cycle is either a memory or an I/O cycle. A Low
on this signal indicates that the current cycle is an I/O
cycle.
W/R
Local Bus Write/Read (Output; Active Low)
This signal indicates to the local bus devices that the
current cycle is either a Read or a Write cycle. A Low
on this signal indicates that the current cycle is a Read
cycle.
A23–A12
Local Bus Upper Address Lines (Output)
These signals are the local bus CPU address lines
when in Local Bus mode. These signals are combined
with the SA11–SA0 signals to form the complete CPU
address bus during local bus cycles.
MAXIMUM ISA BUS INTERFACE
The pins listed below as part of the “ISA Bus Interface”
are available when the ÉlanSC310 microcontroller pin
configuration is configured to enable the maximum ISA
Bus. When the maximum ISA bus interface is enabled,
the CPU local bus interface is disabled. (This mode
does not support master and ISA refresh cycles.)
For more information, see “Maximum ISA Interface ver-
sus Local Bus Interface” on page 60, and Tables 33
and 34 on page 63 and the Élan
Élan
Note , order #20747.
0WS
Zero Wait State (Input; Active Low)
This input can be driven active by an ISA memory de-
vice to indicate that it can accept a Zero Wait State
memory cycle.
BALE
Bus Address Latch Enable (Output; Active High)
This PC/AT-compatible signal is used by external de-
vices to latch the LA signals for the current cycle.
DACK7, DACK6, DACK5, DACK3, DACK2, DACK1,
DACK0
DMA Acknowledge (Output; Active Low)
DMA acknowledge signals are active Low output pins
that acknowledge their corresponding DMA requests.
36
TM
SC310 Devices’ ISA Bus Anomalies Application
Élan™SC310 Microcontroller Data Sheet
TM
SC300 and
P R E L I M I N A R Y
Note: The DACK1, DACK2, and DACK5 signals are
also available in Local Bus mode.
DRQ7, DRQ6, DRQ5, DRQ3, DRQ2, DRQ1, DRQ0
DMA Request (Input; Active High)
DMA Request signals are asynchronous DMA channel
request inputs used by peripheral devices to gain ac-
cess to a DMA service.
Note:
available in the local bus pin configuration.
IOCHCHK
I/O Channel Check (Input; Active Low)
This is a PC/AT-compatible signal used to generate an
NMI or SMI.
Note: IOCHCHK is also available in the Local Bus pin
configuration.
IRQ15, IRQ14, IRQ12–IRQ9, IRQ7–IRQ3, IRQ1
Interrupt Request
(Inputs; Rising Edge/Active High Trigger)
Interrupt Request input pins signal the internal 8259
compatible interrupt controller that an I/O device needs
servicing. IRQ3 and IRQ6 are shared with PIRQ0 and
PIRQ1.
IRQ0 is internally connected to the counter/timer, IRQ2
is used for cascading, and IRQ8 is connected to the
RTC. IRQ13 is reserved. IRQ0, IRQ2, IRQ8, and
IRQ13 are not available externally.
Note: IRQ4, IRQ12, and IRQ15 are also available in
the Local Bus pin configuration.
LA23–LA17
Latchable ISA Address Bus (Outputs)
These are the ISA latchable address signals. These
signals are valid early in the bus cycle so that external
peripherals may have time to decode the address and
return certain control feedback signals such as
MCS16.
LMEG
Address is in Low Meg (Output; Active Low)
This signal is active (Low) whenever the address for
the current cycle is in the first Mbyte of memory ad-
dress space (SA23 = SA22 = SA21 = SA20 = 0).
Note:
or SMEMW. Instead, address lines SA23–SA20 should
be decoded. For more information about
Élan
Anomalies Application Note , order #20747.
TM
The
LMEG
SC300 and Élan
DRQ1, DRQ2, and DRQ5 signals are also
should not be used to generate SMEMR
TM
SC310 Devices’ ISA Bus
LMEG
, see the