ELANSC310 AMD [Advanced Micro Devices], ELANSC310 Datasheet - Page 45

• Manufacturer Part Number: ELANSC310
• Description: Single-Chip, 32-Bit, PC/AT Microcontroller
• Manufacturer: AMD [Advanced Micro Devices]

Notes:
All power management features will be disabled when AC power is detected via the ACIN pin being High. A register is provided
to implement “software ACIN” by writing 1 to bit 5 in the Miscellaneous 6 Register, Index 70h.
The DMA clock can be stopped except during DMA transfers. The Function Enable Register, Index B0h, controls this function.
The CPU clock speed in Low-Speed PLL mode is selectable, (see the PMU Control 3 Register, Index ADh).
The CPU Clock speed:
1. Can be programmed to run intermittently (on IRQ0) at 9.2 MHz.
2. Programmable option (but not on per-clock basis; i.e., all clocks with this note are controlled by a single ON/OFF select for
3. Programmable option, will reflect setting in Suspend mode.
4. Can be programmed to run at 9.2 MHz during temporary-on NMI/SMI handlers.
PMC and PGP Pins
The ÉlanSC310 microcontroller supports five power
management control (PMC) pins and four programma-
ble general purpose (PGP) pins. The PMC pins can be
used to control the VCC rails of peripheral devices. The
PMC pins are related to the operating modes of the
ÉlanSC310 microcontroller PMU. The PGP pins can be
used as general I/O chip selects for various uses.
The PMC4–PMC0 pins are controlled by Configuration
Registers at Indexes 80h, 81h, ABh, and ACh. Each
pin can be programmed to be activated upon entry into
Power On
High-Speed PLL
Low-Speed PLL
Doze
Sleep
Suspend
Off
High-Speed
PLL
Low-Speed
PLL
Doze
Sleep
Suspend
Off
that PMU mode).
Mode
Mode
1.152/0.567 MHz
33/25/20 MHz
High-Speed
4.608/2.304/
After Power-on reset, system enters High-Speed PLL mode.
The system will be in this mode as long as activities are detected by activity monitor (described in the Pro-
grammable Activity Mask Registers, Indexes 08h, 75h, and 76h).
The system will enter this mode from High-Speed PLL mode after a programmable 1/512 s to 1/2 s, or
1/16 s to 16 s of inactivity.
The system will enter this mode from Low-Speed PLL mode after a programmable 1/16 s to 16 s, or
1/2 s to 128 s of inactivity.
The system will enter this mode from Doze mode after a programmable 4 s to 17 minutes of inactivity.
The system will enter this mode from Sleep mode after a programmable 1/16 s to 16 s of inactivity.
The system will enter this mode from Suspend mode after a programmable 1 to 256 minutes of inactivity.
CPU CLK
DC
DC
DC
DC
1
1.152/0.567 MHz
9.2 MHz/DC
9.2 MHz/DC
9.2 MHz/DC
4.608/2.304/
Low-Speed
Élan™SC310 Microcontroller Data Sheet
CPU CLK
9.2 MHz
DC
Table 22. Internal Clock States
1
P R E L I M I N A R Y
Table 21. PMU Modes
4
4
4
14.3 MHz/DC
14.3 MHz/DC
14.3 MHz/DC
14.3 MHz/DC
VIDEO CLK
14.336 MHz
14.336 MHz
any of the PMU modes or driven directly by software.
PMC0 can be activated when the system is in High-
Speed PLL or Low-Speed PLL modes; PMC1 when the
system is in Doze mode; PMC2 when the system is in
Sleep mode; PMC3 and PMC4 when the system is in
Suspend mode; or just about any other combination.
These pins can then be used by the system designer to
shut off power to particular peripherals when the sys-
tem enters certain modes, just as internal clocks are
slowed or stopped in these modes. Upon the rising
edge of RESIN, PMC0, PMC1, PMC2, and PMC4 are
Description
2
2
2
3
4.6 MHz/DC
4.6 MHz/DC
4.6 MHz/DC
DMA CLK
0.58/0.29
4.6 MHz
2.3/1.2/
MHz
DC
1
4
4
4
9.2 MHz/DC
SYSCLK
9.2 MHz
9.2 MHz
DC
DC
DC
2
1.19 MHz/DC
1.19 MHz/DC
1.19 MHz/DC
1.19 MHz/DC
8254 CLK
1.19 MHz
1.19 MHz
(Timer)
2
2
2
3
1.8 MHz/DC
1.8 MHz/DC
1.8 MHz/DC
1.8 MHz/DC
1.8432 MHz
1.8432 MHz
16450 CLK
(UART)
45
2
2
2
3