HY5DU281622DLT HYNIX [Hynix Semiconductor], HY5DU281622DLT Datasheet - Page 15

• Manufacturer Part Number: HY5DU281622DLT
• Description: 128Mb-S DDR SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

CKE FUNCTION TRUTH TABLE
Note :
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All command can be stored after 2 clocks from low to high transition of CKE.
3. Illegal if CK is suspended or stopped during the power down mode.
4. Self refresh can be entered only from the all banks idle state.
5. Disabling CK may cause malfunction of any bank which is in active state.
Rev. 0.0 / Apr. 2003
When CKE=L, all DQ and DQS must be in Hi-Z state.
ANY STATE
ALL BANKS
REFRESH
Current
DOWN
POWER
OTHER
ABOVE
State
IDLE
THAN
SELF
4
2
1
CKEn-
1
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CKEn
H
H
H
H
H
H
H
H
H
H
H
H
H
X
L
X
L
L
L
L
L
L
L
L
L
L
L
/CS
H
H
H
X
L
L
L
L
X
X
L
L
L
L
X
X
L
L
L
L
L
L
X
X
X
X
X
/RAS
X
X
H
H
H
X
X
X
H
H
H
X
X
X
H
H
H
X
X
X
X
X
L
L
L
L
L
/CAS
H
H
H
H
H
H
H
X
X
L
X
X
X
X
L
X
X
X
L
X
L
L
X
X
X
X
X
/WE
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
/ADD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Exit self refresh, enter idle after tSREX
Exit self refresh, enter idle after tSREX
See operation command truth table
See operation command truth table
NOP, continue power down mode
Exit power down, enter idle
Exit power down, enter idle
NOP, continue self refresh
HY5DU28422D(L)T
HY5DU28822D(L)T
HY5DU281622D(L)T
Enter self refresh
Exit power down
Exit power down
ILLEGAL
INVALID
INVALID
INVALID
INVALID
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Action
NOP
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