HY5DU281622DLT HYNIX [Hynix Semiconductor], HY5DU281622DLT Datasheet - Page 26

• Manufacturer Part Number: HY5DU281622DLT
• Description: 128Mb-S DDR SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

DC CHARACTERISTICS II
8Mx16
Rev. 0.0 / Apr. 2003
Operating Current
Operating Current
Precharge Power
Down Standby
Current
Idle Standby Current
Idle Standby Current
Idle Quiet Standby
Current
Active Power Down
Standby Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current -
Four Bank Operation
Random Read
Current
Parameter
Symbol
I
I
I
I
I
I
I
I
I
IDD0
I
DD4W
I
I
I
DD2N
DD2Q
DD3N
DD2P
DD2F
DD3P
DD4R
DD7A
DD1
DD5
DD6
DD7
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice per
clock cycle; address and control inputs changing once per
clock cycle
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once per
clock cycle.
VIN=VREF for DQ, DQS and DM
/CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses
and other control inputs stable, Vin=Vref for DQ, DQS and
DM
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock
cycle
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per
clock cycle
tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz
CKE =< 0.2V; External clock on;
tCK=tCK(min)
Four bank interleaving with BL=4, Refer to the following
page for detailed test condition
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA,
100% DQ, DM and DQS inputs changing twice per clock
cycle; 100% addresses changing once per clock cycle
(TA=0 to 70
Test Condition
o
C, Voltage referenced to V
Low Power
Normal
SS
= 0V)
-D4
HY5DU28422D(L)T
HY5DU28822D(L)T
HY5DU281622D(L)T
Speed
120
120
170
190
180
260
260
10
60
60
50
10
65
2
1
-D43
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
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