HY5DU281622DLT HYNIX [Hynix Semiconductor], HY5DU281622DLT Datasheet - Page 9

• Manufacturer Part Number: HY5DU281622DLT
• Description: 128Mb-S DDR SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

SIMPLIFIED COMMAND TRUTH TABLE
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting duing Extended MRS or MRS.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
Rev. 0.0 / Apr. 2003
Precharge Power
Extended Mode Register Set
(tWR) is needed to guarantee that the last data has been completely written.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
to activated bank until CK(n+BL/2+tRP).
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
precharged.
Write with Autoprecharge
Read with Autoprecharge
Active Power
Precharge selected Bank
Self Refresh
Down Mode
Down Mode
Precharge All Banks
Mode Register Set
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Read Burst Stop
Device Deselect
No Operation
Auto Refresh
Bank Active
Command
Write
Read
Entry
Entry
Entry
Exit
Exit
Exit
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
CKEn
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
CS
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
H
H
H
H
H
H
H
X
X
X
X
X
V
L
L
L
L
L
L
X
CAS
H
H
H
H
H
H
H
X
X
X
X
X
V
L
L
L
L
L
L
WE
H
H
H
H
H
H
H
H
L
L
X
L
L
L
X
X
X
X
V
ADDR
CA
CA
X
HY5DU28422D(L)T
HY5DU28822D(L)T
HY5DU281622D(L)T
RA
OP code
OP code
A10/
X
X
X
X
X
X
AP
H
H
H
L
L
L
BA
V
V
V
X
V
Note
1,2
1,2
1,3
1,4
1,5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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