HY5DU281622DLT HYNIX [Hynix Semiconductor], HY5DU281622DLT Datasheet - Page 30

• Manufacturer Part Number: HY5DU281622DLT
• Description: 128Mb-S DDR SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Note :
1.
2.
3.
4.
Rev. 0.0 / Apr. 2003
Input Pulse Width
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
Exit self refresh to non-READ command
Exit self refresh to READ command
Average Periodic Refresh Interval
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
For command/address input slew rate >=1.0V/ns
For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Parameter
V/ns
0.5
0.4
0.3
Delta tIS
+150
+225
ps
0
Symbol
t
t
tXSRD
t
WPREH
t
t
t
t
WPRES
t
t
tXSNR
t
t
t
DQSH
t
WPST
DQSL
DQSS
t
DIPW
RPRE
RPST
t
t
MRD
REFI
IPW
DSH
DSS
DH
DS
Min
0.35
0.35
0.72
1.75
0.25
DDR400 (D4)
200
2.2
0.2
0.2
0.4
0.4
0.9
0.4
0.4
75
0
2
-
Delta tIH
ps
0
0
0
Max
1.28
1.1
0.6
0.6
7.8
-
-
-
-
-
-
-
-
-
-
-
DDR400 (D43)
0.35
0.35
0.72
1.75
0.25
Min
200
2.2
0.2
0.2
0.4
0.4
0.9
0.4
0.4
75
0
2
-
HY5DU28422D(L)T
HY5DU28822D(L)T
HY5DU281622D(L)T
Max
1.28
1.1
0.6
0.6
7.8
-
-
-
-
-
-
-
-
-
-
-
Unit
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
ns
ns
ns
ns
ns
us
-Continue-
6,7,11
12,13
Note
6
6
8
8
,
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