SSTUH32866EC/G,551 NXP Semiconductors, SSTUH32866EC/G,551 Datasheet - Page 9

• Manufacturer Part Number: SSTUH32866EC/G,551
• Description: IC BUFFER 1.8V 25BIT SOT536-1
• Manufacturer: NXP Semiconductors

Specifications of SSTUH32866EC/G,551

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277966551; SSTUH32866EC/G-S; SSTUH32866EC/G-S

Philips Semiconductors
9397 750 14199
Product data sheet
cascaded to the PAR_IN of the second register. The QERR output of the first register is
left floating and the valid error information is latched on the QERR output of the second
register.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock
cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE, DCS, DODT,
and CSR) are not included in the parity check computation.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (floating) data, clock and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and
all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid
logic HIGH or LOW level.
The device also supports low-power active operation by monitoring both system chip
select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states
when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn
and PPO outputs will function normally. The RESET input has priority over the DCS and
CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the
QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can
be hard-wired to ground, in which case, the setup time requirement for DCS would be the
same as for the other Dn data inputs. To control the low-power mode with DCS only, then
the CSR input should be pulled up to V
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the Qn outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUH32866 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
1.8 V high-drive DDR2 configurable registered buffer with parity
Rev. 01 — 13 May 2005
DD
through a pull-up resistor.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SSTUH32866
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