SSTUH32866EC/G,551 NXP Semiconductors, SSTUH32866EC/G,551 Datasheet

IC BUFFER 1.8V 25BIT SOT536-1

SSTUH32866EC/G,551

Manufacturer Part Number
SSTUH32866EC/G,551
Description
IC BUFFER 1.8V 25BIT SOT536-1
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SSTUH32866EC/G,551

Logic Type
1:1, 1:2 Configurable Registered Buffer with Parity
Supply Voltage
1.7 V ~ 1.9 V
Number Of Bits
25, 14
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
96-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935277966551
SSTUH32866EC/G-S
SSTUH32866EC/G-S
1. General description
2. Features
The SSTUH32866 is a 1.8 V configurable register specifically designed for use on DDR2
memory modules requiring a parity checking function. It is defined in accordance with the
JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity
checking function in a compatible pinout. The JEDEC standard for SSTUH32866 is
pending publication. The register is configurable (using configuration pins C0 and C1) to
two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated
as Register A or Register B on the DIMM.
The SSTUH32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs
and indicates whether a parity error has occurred on its open-drain QERR pin
(active LOW). The convention is even parity, that is, valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity input
bit.
The SSTUH32866 is packaged in a 96-ball, 6
package (13.5 mm
The SSTUH32866 is identical to SSTU32866 in function and performance, with
higher-drive outputs optimized to drive heavy load nets (for example, stacked DRAMs)
while maintaining speed and signal integrity.
SSTUH32866
1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable
registered buffer with parity for DDR2 RDIMM applications
Rev. 01 — 13 May 2005
Configurable register supporting DDR2 Registered DIMM applications
Higher output drive strength version of SSTU32866 optimized for high-capacitive load
nets
Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
Controlled output impedance drivers enable optimal signal integrity and speed
Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
Supports up to 450 MHz clock frequency of operation
Optimized pinout for high-density DDR2 module design
Chip-selects minimize power consumption by gating data outputs from changing state
Supports SSTL_18 data inputs
Checks parity on the DIMM-independent data inputs
Partial parity output and input allows cascading of two SSTUH32866s for correct parity
error processing
Differential clock (CK and CK) inputs
5.5 mm).
16 grid, 0.8 mm ball pitch LFBGA
Product data sheet

Related parts for SSTUH32866EC/G,551

SSTUH32866EC/G,551 Summary of contents

Page 1

SSTUH32866 1.8 V high output drive 25-bit 14-bit configurable registered buffer with parity for DDR2 RDIMM applications Rev. 01 — 13 May 2005 1. General description The SSTUH32866 is a 1.8 V configurable ...

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Philips Semiconductors Supports LVCMOS switching levels on the control and RESET inputs Single 1.8 V supply operation Available in 96-ball, 13 Applications DDR2 registered DIMMs desiring parity checking functionality Stacked or planar high-DRAM count registered DIMMs 4. Ordering ...

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Philips Semiconductors 5. Functional diagram (1) Disabled configuration. Fig 1. Functional diagram of SSTUH32866 Register A configuration with and 9397 750 14199 Product data sheet 1.8 V high-drive DDR2 configurable ...

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Philips Semiconductors RESET CK CK D2, D3, D5, D6 D14 VREF C1 PAR_IN C0 Fig 2. Parity logic diagram for Register A configuration (positive logic 9397 750 14199 ...

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Philips Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration for LFBGA96 Fig 4. Ball mapping register ( 9397 750 14199 Product data sheet 1.8 V high-drive DDR2 configurable registered buffer ...

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Philips Semiconductors Fig 5. Ball mapping Register A ( Fig 6. Ball mapping Register B ( 9397 750 14199 Product data sheet 1.8 V ...

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Philips Semiconductors 6.2 Pin description Table 2: Symbol GND V DD VREF RESET CSR DCS D1 to D25 DODT DCKE PAR_IN Q1 to Q25, Q2A to Q14A, Q1B to Q14B PPO QCS, QCSA, QCSB QODT, QODTA, ...

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Philips Semiconductors Table 2: Symbol QERR n.c. DNU [1] Depends on configuration. See [2] Data inputs = D2, D3, D5, D6 D25 when and Data inputs = D2, D3, D5, D6, D8 ...

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Philips Semiconductors cascaded to the PAR_IN of the second register. The QERR output of the first register is left floating and the valid error information is latched on the QERR output of the second register error occurs and ...

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Philips Semiconductors 7.1 Function table Table 3: Function table (each flip-flop LOW voltage level HIGH voltage level don’t care; RESET DCS CSR ...

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Philips Semiconductors 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V receiver input voltage I V driver output voltage O I input clamp current IK ...

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Philips Semiconductors Table 6: Recommended operating conditions Symbol Parameter I HIGH-level output current OH I LOW-level output current OL T ambient temperature amb [1] The RESET and Cn inputs of the device must be held at valid levels (not floating) ...

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Philips Semiconductors Table 8: Timing requirements At recommended operating conditions (see Symbol Parameter f clock frequency clock t pulse duration, CK, CK HIGH W or LOW t differential inputs active time ACT t differential inputs inactive time INACT t setup ...

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Philips Semiconductors 10.1 Timing diagrams RESET DCS CSR D25 Q25 PAR_IN PPO QERR Fig 7. Timing diagram for SSTUH32866 used as a single device 9397 ...

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Philips Semiconductors RESET DCS CSR D14 Q14 PAR_IN PPO QERR (not used) Fig 8. Timing diagram for the first SSTUH32866 ( Register A configuration) device used in pair; C0 ...

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Philips Semiconductors RESET DCS CSR D14 Q14 (1) PAR_IN PPO (not used) QERR (1) PAR_IN is driven from PPO of the first SSTUH32866 device. Fig 9. Timing diagram for the second ...

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Philips Semiconductors 11. Test information 11.1 Parameter measurement information for data output load circuit All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at ...

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Philips Semiconductors Fig 13. Voltage waveforms; setup and hold times Fig 14. Voltage waveforms; propagation delay times (clock to output) Fig 15. Voltage waveforms; propagation delay times (reset to output) 9397 750 14199 Product data sheet 1.8 V high-drive DDR2 ...

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Philips Semiconductors 11.2 Data output slew rate measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 16. Load circuit, HIGH-to-LOW slew measurement Fig 17. ...

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Philips Semiconductors 11.3 Error output load circuit and voltage measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 20. Load circuit, error output measurements ...

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Philips Semiconductors Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to 11.4 Partial parity out load circuit and voltage measurement information All input pulses are supplied by generators having the following characteristics: ...

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Philips Semiconductors Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to 9397 750 14199 Product data sheet 1.8 V high-drive DDR2 configurable registered buffer with parity LVCMOS RESET output ...

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Philips Semiconductors 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm ball A1 index area ...

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Philips Semiconductors 13. Soldering 13.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...

Page 25

Philips Semiconductors – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, ...

Page 26

Philips Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, ...

Page 27

Philips Semiconductors 16. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

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Philips Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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