XRT91L82ES Exar, XRT91L82ES Datasheet - Page 10

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XRT91L82ES

Manufacturer Part Number
XRT91L82ES
Description
Bus Transceivers Transceiver
Manufacturer
Exar
Datasheet

Specifications of XRT91L82ES

Product Category
Bus Transceivers
Rohs
yes
XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
COMMON CONTROL
LOOPTM_NOJA
DLOOP
N
/ SDI
AME
LVCMOS
LVCMOS
LVTTL,
LVTTL,
L
EVEL
T
YPE
I
I
C10
E11
P
IN
PRELIMINARY
Digital Local Loopback
The digital local loopback mode interconnects the 16-bit parallel
transmit data and parallel transmit clock input to the 16-bit par-
allel receive data and parallel receive clock output respectively
while maintaining the transmit serial data output. If digital local
loopback is enabled, the receive serial data input is ignored.
"Low" = Digital Local Loopback Mode Enabled
"High" = Disabled
This pin is provided with an internal pull-up.
Loop Timing Mode With No Jitter Attenuation
Hardware Mode When the loop timing mode is activated, the
external local reference clock input to the CMU is replaced with
the 1/16th of the high-speed recovered receive clock coming
from the CDR.
"Low" = Disabled
"High" = Loop timing Activated
This pin is provided with an internal pull-down.
Host Mode This pin is functions as the microprocessor Serial
Data Input.
7
D
ESCRIPTION
xr
xr
xr
xr
REV. P1.0.5

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