XRT91L82ES Exar, XRT91L82ES Datasheet - Page 51

• Manufacturer Part Number: XRT91L82ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L82ES

• Product Category: Bus Transceivers
• Rohs: yes

xr
xr
xr
xr
REV. P1.0.5
B
D3
D2
D1
D0
IT
B
D7
D6
D5
D4
D3
D2
D1
D0
IT
SEREFDIS
POLARITY
TXSWING
INTERM
Device "ID"
N
AME
N
MSB
AME
T
ABLE
Transmit Parallel Bus Input Internal Termination
Provides 100 line-to-line internal termination to TXDI[15:0]P/N
and TXPCLKIP/N.
"Low" = Disabled
"High" = TXDI[15:0]P/N and TXPCLKIP/N internally terminated.
SE_REF Power down Control
Powers down SE_REF and reduces power consumption.
"0" = SE_REF Enabled
"1" = SE_REF Disabled
Serial CML Optical Transceiver Swing Select
This bit is used to select the output swing of the high-speed CML
interface to the optical transceiver.
"0" = Low Swing Mode CML Output Selected
"1" = High Swing Mode CML Output Selected
See Table 12 in “Section 3.9, Transmit Serial Output Control” on
page 28.
Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"0" = SDEXT is active "Low"
"1" = SDEXT is active "High"
The device "ID" of the XRT91L82 LIU is 0x8003h. Along with the
revision "ID", the device "ID" is used to enable software to identify
the silicon adding flexibility for system control and debug.
22: M
C
ICROPROCESSOR
ONFIGURATION
D
EVICE
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
"ID" R
C
F
F
ONTROL
UNCTION
UNCTION
R
48
EGISTER
EGISTER
R
EGISTER
(0
0
X
X
3C
3C
H
(0
H
)
X
B
07
IT
H
D
)
ESCRIPTION
Register
Register
Type
Type
R/W
R/W
R/W
R/W
RO
XRT91L82
(HW reset)
(HW reset)
Default
Default
Value
Value
0
1
1
1
1
0
0
0
0
0
0
0