XRT91L82ES Exar, XRT91L82ES Datasheet - Page 33

• Manufacturer Part Number: XRT91L82ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L82ES

• Product Category: Bus Transceivers
• Rohs: yes

xr
xr
xr
xr
REV. P1.0.5
RLOOPS_PRBSCLR is a dual function pin that serves as both serial remote loopback enable and PRBS error
clear function. The serial remote loopback function is activated by setting RLOOPS_PRBSCLR "Low". When
serial remote loopback is activated, the high-speed serial receive data from RXIP/N is presented at the high-
speed transmit output TXOP/N, and the high-speed recovered clock is selected and presented to the high-
speed transmit clock output TXSCLKOP/N. During serial remote loopback, the high-speed receive data (RXIP/
N) is also converted to parallel data and presented at the low-speed receive parallel interface RXDO[15:0]P/N.
The recovered receive clock is also divided by 16 and presented at the low-speed clock output RXPCLKOP/N
to synchronize the transfer of the 16-bit received parallel data. In PRBS Test Mode, serial remote loopback is
not available when the PRBS generator and analyzer is enabled. This pin serve as the PRBS error clear
(PRBSCLR) function to reset the PRBS_ERR error output indicator. A simplified block diagram of serial
remote loopback is shown in Figure 18.
F
RLOOPP controls a more comprehensive version of remote loopback that can also be used in conjunction with
the de-jitter PLL that is phase locked to the recovered receive clock. In this mode, the received signal is
processed by the CDR, and is sent through the serial to parallel converter. At this point, the 16-bit parallel data
and clock are looped back to the transmit FIFO. Concurrently, if receive clock jitter attenuation is also
employed, the received clock is divided down in frequency and presented to the input of the integrated phase/
frequency detector and is compared to the frequency of a VCXO that is connected to the VCXO_IN input. With
the LOOPTM_JA configured to use the recovered receive clock as the reference and VCXO_SEL asserted,
the VCXO is phase locked to the recovered receive clock. The de-jittered clock is then used to retime the
transmitter, resulting in the re-transmission of the de-jittered received data out of TXOP/N. A FIFO reset using
FIFO_RST should follow immediately after enabling/disabling parallel remote loopback. A simplified block
diagram of parallel remote loopback is shown in Figure 19.
F
4.0 DIAGNOSTIC FEATURES
4.1
4.2
IGURE
IGURE
18. S
19. P
Serial Remote Loopback
Parallel Remote Loopback (Host Mode Only)
ERIAL
ARALLEL
RX Parallel Output
RX Parallel Output
R
EMOTE
R
EMOTE
L
OOPBACK
L
Serial Remote Loopback
OOPBACK
Parallel Remote Loopback
FIFO
FIFO
PISO
SIPO
PISO
SIPO
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
30
Re-Timer
Re-Timer
CDR
CDR
Output Drivers
Output Drivers
Input Drivers
Input MUX
CML
CML
CML
CML
TX Serial Output
RX Serial Input
TX Serial Output
RX Serial Input
XRT91L82