XRT91L82ES Exar, XRT91L82ES Datasheet - Page 58

• Manufacturer Part Number: XRT91L82ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L82ES

• Product Category: Bus Transceivers
• Rohs: yes

XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REVISION HISTORY
R
EVISION
P1.0.3
#
March 2005
D
ATE
1.Moved microprocessor SDI pin from D10 to pin C10 and SCLK from D4 to pin
D12.
2.Moved CP_OUT from pin F14 pin to pin F1 for Host Mode operation only.
3.Moved VCXO_IN from pin E14 to pin E4.
4.Removed IN_TERM in pin E4 to reflect enhanced internal bus termination sup-
port.
5.Added RXCAP1P and RXCAP1N/CP_OUT on pins E1 and F1 for external loop
filter capacitors.
5.Added XRES1P and XRES1N LVDS biasing external resistors on pins E14 and
F14.
6.Renamed RESETB, TXSCLKODIS, FIFO_RST/SCLK, REFREQSEL1,
SEREF_EN, RLOOPS/PRBS_CLEAR, DLOOP, TX_SWING, TEST_MODE,
PRBS_NOLOCK, RXCLKP/N, RXLCKREF, DISRD, DISRDCLK, LOSEXT pins to
RESET, TXSCLKOOFF, FIFO_RST, REFREQSEL1/SCLK, SEREF_DIS,
RLOOPS_PRBSCLR, DLOOP, TXSWING, PRBS_EN, PRBS_ERR, RXP-
CLKOP/N, RXLCKREF, DISRD, DISRDCLK, SDEXT respectively to reflect active
low assertion and more precise functionality.
7.Renamed and updated bit description of VDD_3.3 to VDD_IO for 3.3V LVPECL
/1.8V LVDS I/O references.
8.Updated STBGA pinout to include above mentioned changes.
9.Retouched 91L82 Block Diagram.
10.Corrected RXDO[15:0]P/N description error from ’updated on rising edge’ to
’updated on falling edge’ of RXPCLKOP/N.
11.Corrected PRBS_EN, FIFO_RST, TXSCLKOOFF description errors .
12.Removed unsupported note for transparent mode FIFO operation in section
3.3 and enhanced and corrected FIFO reset operation description.
13.Corrected Figure 14, “Loop Timing Mode Using an External Cleanup VCXO
(Host Mode Only)
14.Added CMU and CDR performace tables.
15.Added CML input swing characteristics.
16.Added external loop filter and LVDS biasing resistor diagrams.
17.Added Data Latency in section 1.0.
18.Updated transmit and receive timing diagrams and timing table specifications.
19.Removed all references to limiting amplifier.
20.Significantly enhanced Signal Detection/LOS section description.
21.Change MHz to Mbps to reflect Parallel data I/O and Serial I/O more accu-
rately. Corrected and enhanced PISO and SIPO diagrams.
22.Added JTAG input pin pull-up and pull-down descriptions.
23.Moved FIFO figure from sect 3.6 to section 3.3.
24.Enlarged CML output swing figure.
25.Added directional arrows for RXIP/N and TXOP/N.
26.Added place holders for jitter performance charts.
27.Reformatted AC/DC electrical characteristics tables.
28.Rearrange Pin List format and formatted Table Header shading.
29.Added cross-reference for register bits and corrected mispellings and
retouched bit descriptions.
30.Updated Microprocessor Register Bits and Descriptions to reflect changes.
31.Changed OC-48 to STS-48 name.
PRELIMINARY
55
D
ESCRIPTION
xr
xr
xr
xr
REV. P1.0.5