XRT91L82ES Exar, XRT91L82ES Datasheet - Page 4

• Manufacturer Part Number: XRT91L82ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L82ES

• Product Category: Bus Transceivers
• Rohs: yes

XRT91L82
REV. P1.0.5
GENERAL DESCRIPTION .................................................................................................1
T
PIN DESCRIPTIONS ..........................................................................................................4
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................16
2.0 RECEIVE SECTION .............................................................................................................................18
3.0 TRANSMIT SECTION ..........................................................................................................................23
ABLE OF
APPLICATIONS ...........................................................................................................................................1
FEATURES
COMMON
T
RECEIVER SECTION
SERIAL MICROPROCESSOR INTERFACE .............................................................................................14
JTAG ..........................................................................................................................................................15
...................................................................................................................................................................14
RANSMITTER
PRODUCT ORDERING INFORMATION ..................................................................................................2
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 16
1.2 CLOCK INPUT REFERENCE ......................................................................................................................... 16
1.3 ALTERNATE CLOCK INPUT REFERENCE (HOST MODE ONLY) .............................................................. 16
1.4 DATA LATENCY ............................................................................................................................................. 17
1.5 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 17
1.6 PRBS PATTERN GENERATOR AND ANALYZER ....................................................................................... 17
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 18
2.2 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 19
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 19
2.4 EXTERNAL SIGNAL DETECTION ................................................................................................................. 20
2.5 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 21
2.6 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 21
2.7 RECEIVE PARALLEL INTERFACE LVDS OPERATION .............................................................................. 22
2.8 PARALLEL RECEIVE DATA OUTPUT DISABLE/MUTE UPON LOSD ........................................................ 22
2.9 PARALLEL RECEIVE CLOCK OUTPUT DISABLE ...................................................................................... 22
2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 22
3.1 TRANSMIT PARALLEL INTERFACE ............................................................................................................ 23
3.2 TRANSMIT PARALLEL DATA INPUT TIMING ............................................................................................. 24
3.3 TRANSMIT FIFO ............................................................................................................................................. 24
3.4 FIFO CALIBRATION UPON POWER UP ....................................................................................................... 25
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 25
F
F
T
T
T
F
F
T
F
T
T
F
F
F
F
T
F
F
T
T
F
F
IGURE
IGURE
ABLE
ABLE
ABLE
IGURE
IGURE
ABLE
IGURE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
ABLE
IGURE
IGURE
1: R
2: A
3: D
4: D
5: C
6: LOSD D
7: R
8: T
9: T
1. B
2. 196 BGA P
3. S
4. R
5. E
6. S
7. R
8. LVDS
9. R
10. T
11. T
12. T
13. S
C
......................................................................................................................................................2
CONTROL
ONTENTS
RANSMIT
RANSMIT
LTERNATE
EFERENCE
ATA INGRESS TO DATA EGRESS LATENCY
IFFERENTIAL
LOCK AND
ECEIVE
LOCK
IMPLIFIED
ECEIVE
XTERNAL
IMPLIFIED
ECEIVE
ECEIVE
S
RANSMIT
RANSMIT
RANSMIT
IMPLIFIED
ECTION
EXTERNAL BIASING RESISTORS
D
ECLARATION
.......................................................................................................................................11
P
IAGRAM OF
S
P
P
P
P
ARALLEL
R
ERIAL
L
D
ARALLEL
ARALLEL
ARALLEL
ARALLEL
.....................................................................................................................................4
F
B
B
INOUT OF
P
P
FIFO
OOP
EFERENCE
ATA
B
REQUENCY
LOCK
LOCK
CML I
ARALLEL
ARALLEL
..................................................................................................................................8
LOCK
............................................................................................................
I
R
F
NPUT
AND
ILTER
D
D
ECOVERY
D
NPUT
O
O
D
C
D
XRT91L82 ...................................................................................................................................... 1
P
ATA AND
IAGRAM OF
IAGRAM OF
THE XRT91L82 (T
UTPUT
UTPUT
ATA AND
LOCK
OLARITY
IAGRAM OF
I
I
S
NPUT
NPUT
I
F
NTERFACE
YSTEM
O
................................................................................................................................................ 19
REQUENCY
S
PTIONS
WING
O
U
I
T
I
T
NTERFACE
C
UTPUT
NTERFACE
IMING
NIT
IMING
S
C
TABLE OF CONTENTS
LOCK
I
F
SIPO ........................................................................................................................... 21
NTERFACE
ETTING
LOCK
P
ORWARD
PISO ......................................................................................................................... 25
(N
P
ARAMETERS
B
ERFORMANCE
.............................................................................................................................. 22
.............................................................................................................................. 24
ORMAL
O
T
LOCK
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
............................................................................................................................. 22
O
IMING
I
PTIONS
PRELIMINARY
UTPUT
NPUT
......................................................................................................................... 20
B
B
....................................................................................................................... 17
OP
LOCK
LOCK
..................................................................................................................... 18
E
.................................................................................................................... 25
M
S
RROR
V
T
PECIFICATION
ODE
T
(N
IMING
IEW
.............................................................................................................. 18
IMING
............................................................................................................. 21
............................................................................................................. 23
ORMAL
.......................................................................................................... 20
).......................................................................................................... 3
/ FEC
C
ORRECTION
S
I
S
PECIFICATION
PECIFICATIONS
M
RATE
ODE
........................................................................................... 24
)...................................................................................... 16
/ FEC
.................................................................................... 17
............................................................................... 24
RATE
........................................................................... 22
) ................................................................... 17
xr
xr
xr
xr
I