XRT91L82ES Exar, XRT91L82ES Datasheet - Page 12

• Manufacturer Part Number: XRT91L82ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L82ES

• Product Category: Bus Transceivers
• Rohs: yes

TRANSMITTER SECTION
XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
TXSCLKOOFF
TXSCLKOP
TXSCLKON
TXPCLKOP
TXPCLKON
/ VCXO_IN
TXPCLKIN
TXPCLKIP
INTERM
N
/ CS
AME
Diff and SE
Diff and SE
CMLDIFF
LVCMOS
LVCMOS
LVCMOS
LVPECL
LVPECL
LVTTL,
LVTTL,
LVDS,
LVDS,
L
/ SE-
EVEL
T
YPE
O
O
I
I
I
P11
P10
P
C9
A9
A8
E4
P8
P7
IN
PRELIMINARY
2.488/2.666 GHz Transmit Serial Clock Output
A high-speed 2.488/2.666 GHz Transmit serial clock output that
can be used to retime TXOP/N.
2.488/2.666 GHz Hi-speed Serial Clock Output Tristate
Hardware Mode Tristates TXSCLKOP/N output and reduces
power consumption.
"Low" = TXSCLKOP/N output Enabled
"High" = Tristates TXSCLKOP/N output
This pin is provided with an internal pull-up.
Host Mode This pin is functions as the microprocessor Chip
Select Input.
Transmit Parallel Bus Input Internal Termination
Hardware Mode Provides 100 line-to-line internal termina-
tion to TXDI[15:0]P/N and TXPCLKIP/N.
"Low" = Disabled
"High" = TXDI[15:0]P/N and TXPCLKIP/N internally terminated.
This pin is provided with an internal pull-down.
Host Mode - Voltage Controled 77.76/83.31 MHz or 155.52/
166.63 MHz External Oscillator Input
This 77.76/83.31 MHz or 155.52/166.63 MHz Single-Ended
LVCMOS clock input is used for the transmit PLL jitter attenua-
tion. ALTFREQSEL register bit determines the value used as
the reference. Software register bit VCXOSEL allows the selec-
tion of the De-Jitter VCXO Mode. See ALTFREQSEL and
VCXO_SEL software register bit description for more details.
Transmit Parallel Clock Input
155.52 MHz clock input used to sample the 16-bit parallel trans-
mit data input TXDI[15:0]P/N. TXPCLKIP/N 100
mination is controlled by INTERM pin or register bit.
TXPCLKIP/N inputs are internally biased to VDD_IO - 1V for
AC coupled application.
N
Transmit Parallel Clock Output
This 155.52 MHz clock can be used for the downstream device
to generate the TXDI[15:0]P/N data and TXPCLKIP/N clock
input. This enables the downstream device and the STS-48
transceiver to be in synchronization.
N
OTE
OTE
9
: The XRT91L82 can accept a 166.63 MHz transmit clock
: The XRT91L82 can output a 166.63 MHz transmit clock
input for Forward Error Correction (FEC) Applications.
output for Forward Error Correction (FEC).
D
ESCRIPTION
xr
xr
xr
xr
internal ter-
REV. P1.0.5