XRT91L82ES Exar, XRT91L82ES Datasheet - Page 13

• Manufacturer Part Number: XRT91L82ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L82ES

• Product Category: Bus Transceivers
• Rohs: yes

TRANSMITTER SECTION
xr
xr
xr
xr
REV. P1.0.5
LOCKDET_CMU
TXCLKO16SEL
TXCLKO16P
TXCLKO16N
OVERFLOW
FIFO_RST
N
AME
Diff and SE
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVPECL
LVTTL,
LVTTL,
L
LVDS,
EVEL
T
YPE
O
O
O
I
I
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
P
C4
C6
D6
D5
P2
P1
IN
Auxiliary Clock Output (155.52/19.44 MHz)
155.52 or 19.44 MHz auxiliary clock derived from CMU output.
This clock can also be used for the downstream device as a ref-
erence for generating the TXDI[15:0]P/N data and TXPCLKIP/
N clock input. This enables the downstream device and the
STS-48 transceiver to be in synchronization. The frequency
output of this pin is controlled by TXCLKO16SEL.
N
Auxiliary Clock Output Select
This pin is used to select the auxiliary clock output.
"Low" = TXCLKO16P/N outputs 155.52/ 166.63 MHz
"High" = TXCLKO16P/N outputs 19.44/ 20.83 MHz
This pin is provided with an internal pull-down.
CMU Lock Detect
This pin is used to monitor the lock condition of the clock multi-
plier unit.
"Low" = CMU Out of Lock
"High" = CMU Locked
Transmit FIFO Overflow
This pin is used to monitor the transmit FIFO status.
"Low" = Normal Status
"High" = Overflow Condition
FIFO Control Reset
FIFO_RST should be held "High" for a minimum of 2 TXP-
CLKOP/N cycles after powering up and during manual FIFO
reset. After the FIFO_RST pin is returned "Low," it will take 8 to
10 TXPCLKOP/N cycles for the FIFO to flush out. Upon an
interrupt indication that the FIFO has an overflow condition, this
pin is used to reset or flush out the FIFO.
"Low" = Normal Operation
"High" = Manual FIFO Reset
This pin is provided with an internal pull-down.
N
1.
2.
OTE
OTES
10
In Hardware Mode, to automatically reset the FIFO, tie the
OVERFLOW output pin to the FIFO_RST input pin or if
desired, an asynchronous FIFO reset pin and the OVER-
FLOW output pin can be logically ’OR’ed and the output
tied to the FIFO_RST input pin.
In Host Mode, this pin is disabled and not used.
FIFO_RST is asserted through Microprocessor Control
Register 0x03
available on Microprocessor Control Register 0x03
D1.
: This pin can output a 166.63/20.83 MHz transmit clock
:
output for Forward Error Correction (FEC).
H
Bit-D0. A FIFO_AUTORST bit is also
D
ESCRIPTION
XRT91L82
H
Bit-