PCAL6408AHKX NXP Semiconductors, PCAL6408AHKX Datasheet
PCAL6408AHKX
Specifications of PCAL6408AHKX
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PCAL6408AHKX Summary of contents
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PCAL6408A Low-voltage translating, 8-bit I with interrupt output, reset, and configuration registers Rev. 2 — 6 December 2012 1. General description The PCAL6408A is an 8-bit general-purpose I/O expander that provides remote I/O expansion for most microcontroller families via the ...
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... NXP Semiconductors The system master can reset the PCAL6408A in the event of a time-out or other improper operation by asserting a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the I causes the same reset/initialization to occur without de-powering the part. ...
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... Ordering options Table 2. Ordering options Type number Orderable part number PCAL6408ABS PCAL6408ABSHP PCAL6408APW PCAL6408APWJ PCAL6408AHK PCAL6408AHKX PCAL6408A Product data sheet Low-voltage translating, 8-bit I Package Name Description HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 3 0.85 mm TSSOP16 plastic thin shrink small outline package ...
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... NXP Semiconductors 4. Block diagram ADDR V DD(I2C-bus) V RESET Fig 1. PCAL6408A Product data sheet Low-voltage translating, 8-bit I INT LP FILTER SCL 2 INPUT I C-BUS FILTER CONTROL SDA DD(P) POWER-ON RESET V SS All I/Os are set to inputs at reset. Block diagram (positive logic) All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning V DD(I2C-bus) ADDR RESET Fig 2. Fig 4. PCAL6408A Product data sheet Low-voltage translating, 8-bit PCAL6408APW 002aah086 Pin configuration for TSSOP16 terminal 1 index area RESET ...
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... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin TSSOP16 HVQFN16 DD(I2C-bus) ADDR 2 16 RESET INT 13 11 SCL 14 12 SDA 15 13 ...
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... NXP Semiconductors 6. Voltage translation Table C-bus and the PCAL6408A. Table 4. V DD(I2C-bus) 1.8 V 1.8 V 1.8 V 1.8 V 2.5 V 2.5 V 2.5 V 2.5 V 3.3 V 3.3 V 3 Functional description Refer to 7.1 Device address The address of the PCAL6408A is shown in Fig 5. ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW (logic 0) to assign one of the two possible slave addresses ...
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... NXP Semiconductors 7.2 Interface definition Table 5. Byte 2 I C-bus slave address I/O data bus 7.3 Pointer register and command byte Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCAL6408A. Two bits of this data byte state the operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that will be affected ...
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... NXP Semiconductors 7.4 Register descriptions 7.4.1 Input port register (00h) The Input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port register is read only; writes to this register have no effect. The default value ‘X’ ...
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... NXP Semiconductors 7.4.5 Output drive strength registers (40h, 41h) The Output drive strength registers control the output drive level of the GPIO. Each GPIO can be configured independently to a certain output current level by two register control bits. For example, Port 7 is controlled by register 41 CC7 (bits [7:6]), Port 6 is controlled by register 41 CC6 (bits [5:4]). The output drive level of the GPIO is programmed 00b = 0.25 ...
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... NXP Semiconductors Table 13. Bit Symbol Default 7.4.7 Pull-up/pull-down enable register (43h) This register allows the user to enable or disable pull-up/pull-down resistors on the I/O pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting the bit to logic 0 disconnects the pull-up/pull-down resistors from the I/O pins. Also, the ...
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... NXP Semiconductors 7.4.10 Interrupt status register (46h) This read-only register is used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of an interrupt. When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return logic 0 ...
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... NXP Semiconductors 7.5 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above V If the I/O is configured as an output enabled, depending on the state of the Output port register. In this case, there are low-impedance paths between the I/O pin and either V recommended levels for proper operation ...
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... NXP Semiconductors 7.6 Power-on reset When power (from applied to V PCAL6408A in a reset condition until V condition is released and the PCAL6408A registers and I initialize to their default states. After that the operating voltage for a power-reset cycle. See requirements”. 7.7 Reset input (RESET) The RESET input can be asserted to initialize the system while keeping the V operating level ...
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... NXP Semiconductors 8. Bus transactions The PCAL6408A PCAL6408A through write and read commands using I lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ...
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... NXP Semiconductors 8.2 Read commands To read data from the PCAL6408A, the bus master must first send the PCAL6408A address with the least significant bit set to a logic 0 (see command byte is sent after the address and determines which register accessed. After a restart the device address is sent again, but this time the LSB is set to a logic 1. ...
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... NXP Semiconductors SCL slave address SDA START condition read from port data into DATA 1 port INT t v(INT) Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode assumed that the command byte has previously been programmed with 00h (read Input port register) ...
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... NXP Semiconductors 9. Application design-in information V = 1.8 V DD(I2C-bus MASTER CONTROLLER SCL SDA RESET V SS Device address configured as 0100 000x for this example. P0 and P2 through P4 are configured as inputs. P1 and P5 through P7 are configured as outputs. (1) Resistors are required for inputs (on P port) that may float driver to an input will never let the input float, a resistor is not needed ...
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... NXP Semiconductors Fig 14. High-value resistor in parallel 9.2 Output drive strength control The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels. By programming these bits the user is changing the number of transistor pairs or ‘ ...
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... NXP Semiconductors Reducing the current drive capability may be desirable to reduce system noise. When the output switches (transitions from H/L), there is a peak current that is a function of the output drive selection. This peak current runs through V and will create noise (some radiated, but more critically Simultaneous Switching Noise (SSN)) ...
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... NXP Semiconductors Table 19. Recommended supply sequencing and ramp rates (unless otherwise noted). Not tested; specified by design. amb Symbol Parameter (dV/dt) fall rate of change of voltage f (dV/dt) rise rate of change of voltage r t reset delay time d(rst) V glitch supply voltage difference DD(gl) t supply voltage glitch pulse width ...
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... NXP Semiconductors 9.4 Device current consumption with internal pull-up and pull-down resistors The PCAL6408A integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails. ...
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... NXP Semiconductors 10. Limiting values Table 20. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter C-bus supply voltage DD(I2C-bus) V supply voltage port P DD(P) V input voltage I V output voltage O I input clamping current IK I output clamping current OK I input/output clamping current ...
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... NXP Semiconductors 12. Thermal characteristics Table 22. Thermal characteristics Symbol Parameter Z transient thermal impedance from junction to ambient th(j-a) [1] The package thermal impedance is calculated in accordance with JESD 51-7. 13. Static characteristics Table 23. Static characteristics + amb DD(I2C-bus) Symbol Parameter V input clamping voltage ...
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... NXP Semiconductors Table 23. Static characteristics + amb DD(I2C-bus) Symbol Parameter I LOW-level output current OL I input current I I HIGH-level input current IH I LOW-level input current IL I supply current DD PCAL6408A Product data sheet Low-voltage translating, 8-bit I …continued = 1. 5.5 V; unless otherwise specified. ...
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... NXP Semiconductors Table 23. Static characteristics + amb DD(I2C-bus) Symbol Parameter I additional quiescent DD [6] supply current C input capacitance i C input/output capacitance io R internal pull-up resistance input/output pu(int) R internal pull-down pd(int) resistance [1] All typical values are at nominal supply voltage (1.8 V, 2 ...
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... NXP Semiconductors 13.1 Typical characteristics (μ 5.5 V DD(P) 5 3.3 V 2 −40 −15 10 Fig 21. Supply current versus ambient temperature (μ 1.5 2.5 3 C T amb Fig 23. Supply current versus supply voltage PCAL6408A Product data sheet Low-voltage translating, 8-bit I 002aag973 ...
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... NXP Semiconductors 35 I sink (mA −40 °C amb 25 ° ° 0 1.65 V DD( sink (mA −40 °C amb 25 ° ° 0 2.5 V DD( sink (mA −40 °C 60 amb 25 °C 85 ° 0 5.0 V DD(P) Fig 25. I/O sink current versus LOW-level output voltage with CCX.X = 11b ...
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... NXP Semiconductors 30 I source (mA −40 °C amb 25 ° ° 0 1.65 V DD( source (mA −40 °C amb 25 ° ° 0 2.5 V DD( source T = −40 °C amb (mA) 25 °C 85 ° 0 5.0 V DD(P) Fig 26. I/O source current versus HIGH-level output voltage with CCX.X = 11b ...
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... NXP Semiconductors 120 V OL (mV) 100 ( (2) 40 (4) 20 (3) 0 −40 − DD(P) sink ( DD(P) sink ( 1 DD(P) sink ( DD(P) sink Fig 27. LOW-level output voltage versus temperature PCAL6408A Product data sheet Low-voltage translating, 8-bit I 002aah056 ...
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... NXP Semiconductors 14. Dynamic characteristics 2 Table 24. I C-bus interface timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Symbol Parameter f SCL clock frequency SCL t HIGH period of the SCL clock HIGH t LOW period of the SCL clock LOW t pulse width of spikes that must ...
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... NXP Semiconductors Table 26. Switching characteristics Over recommended operating free air temperature range; C Symbol Parameter t valid time on pin INT v(INT) t reset time on pin INT rst(INT) t data output valid time v(Q) t data input set-up time su(D) t data input hold time h(D) 15. Parameter measurement information a. SDA load configuration ...
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... NXP Semiconductors a. Interrupt load configuration START condition slave address SDA SCL INT A t v(INT) A data into ADDRESS port INT t v(INT) Pn View Voltage waveforms C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z All parameters and waveforms are not applicable to all devices ...
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... NXP Semiconductors a. P port load configuration SCL SDA Pn b. Write mode (R SCL Pn c. Read mode (R includes probe and jig capacitance measured from 0.7 v(Q) All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. ...
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... NXP Semiconductors V DD(I2C-bus) SDA DUT a. SDA load configuration START SCL SDA RESET t rec(rst RESET timing C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. ...
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... NXP Semiconductors 16. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors XQFN16: plastic, extremely thin quad flat package; no leads; 16 terminals; body 1.80 x 2. terminal 1 index area L terminal 1 index area Dimensions (1) Unit max 0.5 0.05 0.25 mm nom 0.127 0.20 min 0.00 0.15 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline ...
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... NXP Semiconductors 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 36. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCAL6408A Product data sheet Low-voltage translating, 8-bit I maximum peak temperature = MSL limit, damage level temperature minimum peak temperature ...
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... NXP Semiconductors 18. Soldering: PCB footprints Footprint information for reflow soldering of HVQFN16 package (0.105 solder land solder paste deposit solder land plus solder paste occupied area Dimensions 0.50 4.00 4.00 2.20 2.20 12-03-07 Issue date 12-03-08 Fig 37. PCB footprint for SOT758-1 (HVQFN16); reflow soldering PCAL6408A ...
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... NXP Semiconductors Footprint information for reflow soldering of TSSOP16 package solder land occupied area DIMENSIONS 0.650 0.750 7.200 4.500 1.350 Fig 38. PCB footprint for SOT403-1 (TSSOP16); reflow soldering PCAL6408A Product data sheet Low-voltage translating, 8-bit (4x) ...
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... NXP Semiconductors Footprint information for reflow soldering of XQFN16 package 3.15 1.65 placement area solder land solder paste deposit, −0.02 around copper, stencil thickness 0.1 occupied area Fig 39. PCB footprint for SOT1161-1 (XQFN16); reflow soldering PCAL6408A Product data sheet Low-voltage translating, 8-bit I 2.35 2.1 CU 1.65 0.4 (12×) 0.22 CU (16×) ...
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... NXP Semiconductors 19. Abbreviations Table 29. Acronym ESD FET GPIO 2 I C-bus I/O LED LSB MSB PCB POR SMBus 20. Revision history Table 30. Revision history Document ID Release date PCAL6408A v.2 20121206 • Modifications: Table 1 “Ordering • Table 2 “Ordering options” minimum order quantity; column “Topside mark” moved to • ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... PCAL6408A Product data sheet Low-voltage translating, 8-bit I own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 Agile I/O features . . . . . . . . . . . . . . . . . . . . . . . 3 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Voltage translation . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Interface definition . . . . . . . . . . . . . . . . . . . . . . 8 7.3 Pointer register and command byte . . . . . . . . . 8 7.4 Register descriptions . . . . . . . . . . . . . . . . . . . . 9 7 ...