PCAL6408AHKX NXP Semiconductors, PCAL6408AHKX Datasheet - Page 16

• Manufacturer Part Number: PCAL6408AHKX
• Description: Interface - I/O Expanders 8bit I2C/SMBus IO Expander w/Interrupt
• Manufacturer: NXP Semiconductors

Specifications of PCAL6408AHKX

• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: XQFN-16
• Operating Current: 200 mA
• Output Current: 25 mA
• Product Type: I/O Expanders

NXP Semiconductors
PCAL6408A
Product data sheet
Fig 10. Read from register
Fig 11. Read Input port register (non-latched)
data into
port
SDA
INT
(cont.)
read from
Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port
register).
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and
actual data transfer from P port (see
S
START condition
SDA
port
S
(repeated)
START condition
SCL
0
8.2 Read commands
S
START condition
0
t
1
v(INT)
slave address
1
0
1
0
slave address
2
0
1
To read data from the PCAL6408A, the bus master must first send the PCAL6408A
address with the least significant bit set to a logic 0 (see
command byte is sent after the address and determines which register is to be accessed.
After a restart the device address is sent again, but this time the LSB is set to a logic 1.
Data from the register defined by the command byte then is sent by the PCAL6408A (see
Figure 10
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no
limit on the number of data bytes received in one read transmission, but on the final byte
received the bus master must not acknowledge the data.
0
slave address
3
0
0
DATA 1
0
4
0
0
0
acknowledge
5
0
0
acknowledge
from slave
DR
AD
and
R/W
from slave
6
AD
DR
0
0
R/W
DR
7
AD
t
1
Figure
h(D)
A
R/W
All information provided in this document is subject to legal disclaimers.
Figure
8
A
1
0
9
A
acknowledge from slave
0
11).
10).
Rev. 2 — 6 December 2012
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
DATA 2
t
command byte
rst(INT)
0
data from register
DATA (first byte)
Low-voltage translating, 8-bit I
0
data from port
0
DATA 1
0
acknowledge
DATA 3
from slave
1 1/0
t
su(D)
A
A
acknowledge
from master
(cont.)
A
acknowledge from master
DATA 4
data from register
DATA (last byte)
data from port
Figure 5
DATA 4
2
C-bus/SMBus I/O expander
no acknowledge
PCAL6408A
for device address). The
from master
© NXP B.V. 2012. All rights reserved.
DATA 5
1
no acknowledge
from master
NA
INT is cleared by
read from port
STOP not needed
to clear INT
P
STOP
condition
P
002aaf827
STOP
condition
002aaf828
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